VHDL - 分配默认值 [英] VHDL - Assigning Default Values

问题描述

我有以下架构：

architecture datapath of DE2_TOP is

begin
  U1: entity work.lab1 port map ( --error on this line
    clock => clock_50,
    key => key,
    hex6 => hex6,
    hex5 => hex5,
    hex4 => hex4
  );

end datapath;

这种架构显然取决于lab1实体。这是我的lab1实体和架构：

This architecture obviously depends on lab1 entity. Here is my lab1 entity and architecture:

entity lab1 is
    port(
        clock : in std_logic;
        key : in std_logic_vector(3 downto 0);
        hex4, hex5, hex6 : out std_logic_vector(6 downto 0);
        value_counter   : in unsigned(7 downto 0);
        register_counter : in unsigned(3 downto 0)
        );
end lab1;

architecture up_and_down of lab1 is
    signal hex5_value : unsigned(7 downto 0);
        begin
    process(clock)
        begin
            value_counter<="00000000"; --default values?
            register_counter<="0000";
            if rising_edge(clock) then
                if (key(3)='0' and key(2)='0' and key(1)='1' and key(0)='0') then
                    value_counter <= value_counter + "1";   
                elsif (key(3)='0' and key(2)='0' and key(1)='0' and key(0)='1') then  
                    value_counter <= value_counter - "1";   
                end if;
            end if;
            hex5_value <= (value_counter - (value_counter mod 10))/10;
    end process;

end architecture up_and_down;

我得到以下错误：错误（10346）：VHDL错误DE2_TOP.vhd（280）：正式端口或参数value_counter必须在指示的行上具有实际或默认值。在我看来，我已经设置了我的lab1架构中的默认值。任何人都知道问题是什么？

I am getting the following error: Error (10346): VHDL error at DE2_TOP.vhd(280): formal port or parameter "value_counter" must have actual or default value on the indicated line. It seems to me that I have set the default values already in my lab1 architecture. Anyone know what the problem is?

推荐答案

这不是一个默认值它也分配到非法的输入端口。此外，实体在架构之前被编译，所以（非法）赋值还不存在。

That's not a "default value" but an assignment to initialise it. It's also assigning to an input port which is illegal. Also, the entity is compiled before the architecture so the (illegal) assignment doesn't exist yet.

signal value_counter : unsigned(7 downto 0) := (others => 'X'); 

是声明中提供的默认值（或初始值）

is a default value (or initial value), supplied in the declaration

port (
   value_counter   : in unsigned(7 downto 0) := (others => '1'); 

将是输入端口上的默认值，但我从来没有见过。连接在端口映射中的所有输入端口如果这个工作我（略）印象深刻，但可能不够快乐关于未连接的输入;似乎太容易忽视的错误。

would be a default value on an input port, but I've never seen that done. I've always connected all input ports in the port map. If this works I'm (slightly) impressed, but probably not enough to be happy about unconnected inputs; it seems too easy to overlook mistakes that way.

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