解释ARM（特别是移动）外设寻址和总线架构？ [英] Explaination of ARM (especifically mobile) Peripherals Addressing and Bus architecture?
问题描述
我试图找出系统总线以及移动设备中出现的各种设备（如传感器芯片，WiFi / BT SoC，触摸屏等）的方式。）由CPU（和其他MCU）寻址。
在PC世界中，我们有总线仲裁器将命令/数据路由到设备， afaik，地址是硬连线在板上（纠正我，如果我错了）。然而，在移动世界中，我没有找到任何这种解决方式的证据;我发现ARM已经标准化了高级微控制器总线架构，但我不知道，虽然该标准是否适用于位于同一SoC（即Exynos，OMAP，Snapdragon等）内的组件（cpu-内核））或影响外设接口。具体来说，我在问什么组件负责分配地址到外围设备和MMIO地址？
更基本的问题是，移动设备中是否存在总线管理设备架构或者也许有某种星拓扑（以CPU为中心）。
从这个问题我得到这样的印象：这些设备被认为是平板设备，即直接连接到CPU而不是通过总线连接的设备。不过，我的问题是操作系统如何知道如何解决这些问题？然后其他线程，此和关于平台设备的此 /驱动程序让我感到困惑..
ARM和x86之间的区别是PIO 。 ARM没有访问I / O设备的特殊说明。一切都是通过内存映射的I / O完成的。
另一个区别是ARM（和RISC一般）具有单独的加载/存储单元，从正常的逻辑。
第三个区别是ARM授权 架构 和逻辑核心。第一个被苹果，三星等公司用于制作洁净室版本的内核的公司使用。对于第二组，谁实际购买逻辑，ARM CPU将包括 AMBA 中的内容家族。
其他来自ARM的外设，如GIC（Cortex-A中断控制器），NVIC（Cortex-M中断控制器），L2控制器，UART等配有AMBA型接口。第三方公司（ChipIdea USB等）也可能会为特定ARM总线设置逻辑。
注意维基百科的AMBA记录了几种总线类型。
- APB - 较低速的外设总线;
- AHB - 几个版本（较旧的北桥）。 li>
- AXI - 较新的多CPU（主）高速总线。示例 NIC301 。
- ACE - 一个AXI扩展名。
/ core可能有一个，两个或更多的主连接到AXI总线。 AXI总线上可能有多个内核。核心的加载/存储和指令获取单元可以使用多个端口将请求分配给单独的从站。 SOC供应商将平衡端口数与期望的内存带宽需求。 GPU也经常连接到AXI总线以及DDR从站。
确实没有100％的标准拓扑;特别是如果您考虑所有未来的ARM设计。然而，典型的拓扑结构将包括顶级的 AXI ，附带一些 AHB 外设。一个或多个二级 APB （总线）将提供对低速外设的访问。不是每个SOC供应商都想花时间重新设计外围设备，而旧的AHB接口速度对于设备来说也许是非常好的。
您的问题被标记为嵌入式linux 的。在大多数情况下，Linux只需要知道物理地址。有时，外设总线控制器可能需要配置。例如，APB可以被配置为允许或不允许用户模式。此配置可能在引导时被锁定。一般来说，Linux不直接关心总线结构。程序员可能已经编写了一个具有结构知识的驱动程序（如IRAM是fasters等）。
但是，我的问题是操作系统知道如何解决这些问题？
较旧的Linux内核将这些定义放在一个机器文件中，并通过平台资源结构，包括中断号和寄存器组的物理地址。在较新的Linux版本中，此信息包含在打开固件或设备树文件中。
具体来说，我在问什么组件负责分配地址到外围设备和MMIO地址？
物理地址设置由SOC制造商。 Linux 平台支持将使用MMU将其映射为不可缓存的某些未使用的范围。通常，物理地址可能非常稀疏，所以虚拟重新映射包更密集。每个人都会导致一个TLB命中（MMU缓存）。
这是一个使用AXI与Cortex- M和Cortex-A连接。
PBRIDGE组件是APB桥接器，并以星形拓扑连接。如其他人所说，您需要查看您的特定SOC文档的具体细节。但是，如果您没有SOC，并且正在尝试一般了解ARM，上面的一些信息将帮助您，无论您有什么SOC。
I will first say that I'm not expert in the field and my question might contain misunderstanding, in which case, I'll be glad if you correct me and attach resources so I can learn further details.
I'm trying to figure out the way that the system bus and how the various devices that appear in a mobile device (such as sensors chips, wifi/BT SoC, touch panel, etc.) are addressed by the CPU (and by other MCUs).
In the PC world we have the bus arbitrator that route the commands/data to the devices, and, afaik, the addresses are hardwired on the board (correct me if I'm wrong). However, in the mobile world I didn't find any evidence of that type of addressing; I did find that ARM has standardized the Advanced Microcontroller Bus Architecture, I don't know, though, whether that standard applied for the components (cpu-cores) which lies inside the same SoC (that is Exynos, OMAP, Snapdragon etc.) or also influence peripheral interfaces. Specifically I'm asking what component is responsible on allocating addresses to peripheral devices and MMIO addresses?
A more basic question would be whether there even exist a bus management in the mobile device architecture or maybe there is some kind of "star" topology (where the CPU is the center).
From this question I get the impression that these devices are considered as platform devices, i.e., devices that are connected directly to the CPU, and not through a bus. Still, my question is how does the OS knows how to address them? Then other threads, this and this about platform devices/drivers made me confused..
A difference between ARM and the x86 is PIO. There are no special instruction on the ARM to access an I/O device. Everything is done through memory mapped I/O.
A second difference is the ARM (and RISC in general) has a separate load/store unit(s) that are separate from normal logic.
A third difference is that ARM licenses both the architecture and logic core. The first is used by companies like Apple, Samsung, etc who make a clean room version of the cores. For the second set, who actually buy the logic, the ARM CPU will include something from the AMBA family.
Other peripherals from ARM such as a GIC (Cortex-A interrupt controller), NVIC (Cortex-M interrupt controller), L2 controllers, UARTs, etc will all come with an AMBA type interface. 3rd party companies (ChipIdea USB, etc) may also make logic that is setup for a specific ARM bus.
Note AMBA at Wikipedia documents several bus types.
- APB - a lower speed peripheral bus; sort of like south bridge.
- AHB - several versions (older north bridge).
- AXI - a newer multi-CPU (master) high speed bus. Example NIC301.
- ACE - an AXI extension.
A single CPU/core may have one, two, or more master connection to an AXI bus. There maybe multiple cores attached to the AXI bus. The load/store and instruction fetch units of a core can use the multiple ports to dispatch requests to separate slaves. The SOC vendor will balance the number of ports with expected memory bandwidth needs. GPUs are also often connected to the AXI BUS along with DDR slaves.
It is true that there is no 100% standard topology; especially if you consider all possible future ARM designs. However, typical topologies will include a top level AXI with some AHB peripherals attached. One or multiple 2nd level APB (buses) will provide access to low speed peripherals. Not every SOC vendor wants to spend time to redesign peripherals and the older AHB interface speeds maybe quite fine for a device.
Your question is tagged embedded-linux. For the most part Linux just needs to know the physical addresses. On occasion, the peripheral BUS controllers may need configuration. For instance, an APB may be configure to allow or disallow user mode. This configuration could be locked at boot time. Generally, Linux doesn't care too much about the bus structure directly. Programmers may have coded a driver with knowledge of the structure (like IRAM is fasters, etc).
Still, my question is how does the OS knows how to address them?
Older Linux kernels put these definitions in a machine file and passed a platform resource structure including interrupt number, and the physical address of a register bank. In newer Linux versions, this information is included with Open Firmware or device tree files.
Specifically I'm asking what component is responsible on allocating addresses to peripheral devices and MMIO addresses?
The physical addresses are set by the SOC manufacturer. Linux platform support will use the MMU to map them as non-cacheable to some un-used range. Often the physical addresses may be very sparse so the virtual remapping pack more densely. Each one incurs a TLB hit (MMU cache).
Here is a sample SOC bus structure using AXI with a Cortex-M and Cortex-A connected.
The PBRIDGE components are APB bridges and it is connected in a star topology. As others suggests, you need to look a your particular SOC documentation for specifics. However, if you have no SOC and are trying to understand ARM generally, some of the information above will help you, no matter what SOC you have.
这篇关于解释ARM（特别是移动）外设寻址和总线架构？的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
