中断的尾线 [英] tail-chaining of Interrupts

问题描述

解决方案

尾连接是对异常的背靠背处理，而不需要中断之间的状态保存和恢复的
开销。
处理器跳过八个寄存器的流行，并在退出一个ISR时输入八个寄存器
，并输入另一个，因为它对堆栈内容没有影响
。
Cortex™-M3技术参考手册

这基本上意味着处理挂起的中断而不重复堆叠。

如果您想了解更多详情，请推荐本书：

ARM Cortex-M3的最终指南

what is tail chaining of Interrupts which is supported by NVIC in ARM Cortex M3.

解决方案

Tail-chaining is back-to-back processing of exceptions without the overhead of state saving and restoration between interrupts. The processor skips the pop of eight registers and push of eight registers when exiting one ISR and entering another because this has no effect on the stack contents. Cortex™-M3 Technical Reference Manual

Which basically means, handling pending interrupts without repeating the stacking.

I recommend this book if you want to know more details:

The Definitive Guide to the ARM Cortex-M3

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