make工具中的变量声明 [英] Variable declaration in make tools

问题描述

让我们有一个简单的 make-file ：

default:
    $(CC) $(FLAGS) $(TARGET) $(TARGET).c

CC=gcc
FLAG= -o
TARGET=binary

变量 CC ， FLAG 和 TARGET 将添加到环境变量数组 make 工具或此变量不依赖于 make 的变量环境。

So does variables CC, FLAG and TARGET will be added to environment variables array of make tool or this variables doesn't depend of make's variable environment?

推荐答案

我不知道你在这里问什么，但是：make保持自己的一组与环境变量完全不同的变量（在环境变量的标准系统定义中）。当make扩展变量（例如 $（CC））时，它使用其make变量集合中的值，而不是环境变量。

I'm not sure what exactly you're asking here, but: make maintains its own set of variables which are entirely separate from "environment variables" (in the standard system definition of environment variables). When make expands a variable (such as $(CC)), it uses the value in its set of "make variables", not "environment variables".

当make启动时，它会将其所有环境变量导入为make变量，以便通过正常的make变量扩展访问它们。

When make starts up, it imports all its environment variables as "make variables" so they can be accessed via normal make variable expansion.

如果更改也是环境一部分的make变量的值，则环境中的值也会更改。此外，当您使用 export 关键字（在GNU make中）时，make将会将该变量放在环境中。

If you change the value of a make variable which is also part of the environment, then the value in the environment is also changed. Also when you use the export keyword (in GNU make) then make will put that variable in the environment as well.

当make运行程序时，它会将环境变量（而不是make变量）传递给运行的程序。

When make runs a program it passes the environment variables, but not the make variables, to the program it's running.

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