如何从VHDL文本文件中的特定行读取 [英] How to read from a specific line from a text file in VHDL

问题描述

我正在用VHDL做一个程序来读写数据。我的程序必须从一行读取数据，处理它，然后将新值保存在旧位置。我的代码有点像：

  WRITE_FILE：进程（CLK）
变量VEC_LINE：行; 
文件VEC_FILE：文本输出results; 
 begin 
 
如果CLK ='0'，则
写入（VEC_LINE，OUT_DATA）; 
 writeline（VEC_FILE，VEC_LINE）; 
 end if; 
结束进程WRITE_FILE; 
  

如果我想读第15行，我该如何指定？然后我想清除第15行，并在那里写一个新的数据。 LINE是访问类型，它会接受整数值吗？

解决方案

罗素的答案 - 使用两个文件 - 就是答案。

找不到第15行（seek）的好方法，但为了VHDL的目的，读取和丢弃前14行是完全合适的。只要把它包装在一个名为seek的程序中，就可以继续进行！

如果你已经在第17行了，你不能倒退，也不能倒退到开始。你可以做的是刷新输出文件（保存开放的行，将其余的输入文件复制到它，关闭这两个文件并重新打开它们，当然这需要VHDL-93而不是VHDL-87文件操作的语法）。只需在一个名为倒带的过程中包装，并继续！

跟踪当前行号，现在您可以寻找第15行，无论您身在何处。

这不是很漂亮，但速度不是很快，但它可以正常工作。这对于VHDL来说已经足够了。换句话说，如果你必须，你可以用VHDL编写一个文本编辑器（忽略交互的问题输入，尽管阅读 stdin 应该可以），但是这个工作有更好的语言。其中一个甚至看起来很像一个面向对象的VHDL ...

I am doing a program in VHDL to read and write data. My program has to read data from a line, process it, and then save the new value in the old position. My code is somewhat like:

WRITE_FILE: process (CLK)
variable VEC_LINE : line;
file VEC_FILE : text is out "results";
 begin

if CLK='0' then
write (VEC_LINE, OUT_DATA);
writeline (VEC_FILE, VEC_LINE);
end if;
end process WRITE_FILE;

If I want to read line 15, how can I specify that? Then I want to clear line 15 and have to write a new data there. The LINE is of access type, will it accept integer values?

解决方案

Russell's answer - using two files - is the answer.

There isn't a good way to find the 15th line (seek) but for VHDL's purpose, reading and discarding the first 14 lines is perfectly adequate. Just wrap it in a procedure named "seek" and carry on!

If you're on the 17th line already, you can't seek backwards, or rewind to the beginning. What you can do is flush the output file (save the open line, copy the rest of the input file to it, close both files and reopen them. Naturally, this requires VHDL-93 not VHDL-87 syntax for file operations). Just wrap that in a procedure called "rewind", and carry on!

Keep track of the current line number, and now you can seek to line 15, wherever you are.

It's not pretty and it's not fast, but it'll work just fine. And that's good enough for VHDL's purposes.

In other words you can write a text editor in VHDL if you must, (ignoring the problem of interactive input, though reading stdin should work) but there are much better languages for the job. One of them even looks a lot like an object-oriented VHDL...

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