vhdl ::使用size参数创建一个类型 [英] vhdl :: creating a type with a size parameter
问题描述
我想知道是否有一种方法可以用VHDL中的size参数定义一个类型。例如：
type count_vector（size：Natural）是无符号的（size-1 downto 0）;
然后再做一些类似的事情
变量int：count_vector（32）：=（others =>'0'）;
变量半字节：count_vector（4）：=（others =>'0'）;
实质上，是否有方法来定义类似数组的类型，还是不允许的通过语法？
我目前正在尝试使用泛型进行重用，但我希望能够充分利用泛型（即：是否有可能在VHDL中编写类型通用实体？
预先感谢！
library ieee;
使用ieee.std_logic_1164.all;
使用ieee.numeric_std.all;
实体foo是
通用（
常量INT_LEFT：自然：= 32;
常量NIB_LEFT：自然：= 4
）;
- note实体声明性项目仅向前看
- 端口声明需要在包中声明的类型或子类型
- 也可以对任何常量使用包
- 类型或子类型可以在此声明为实体声明项：
- 子类型int_size是无符号的（INT_LEFT downto 0）;
- 子类型nib_size是无符号的（NIB_LEFT downto 0）;
最终实体;
foo of foo是
- 或者作为架构声明项目：
子类型int_size是无符号的（INT_LEFT downto 0）;
子类型nib_size是无符号的（NIB_LEFT downto 0）;
begin
USAGE：
process
variable int：int_size：=（others =>'0'）;
变量半字节：nib_size：=（others =>'0'）;
begin
int：= int + 3;
- 函数+是L：UNSIGNED，R：NATURAL
- int_size和nibble_size是UNSIGNED的子类型
报告integer'IMAGE（TO_INTEGER（int））;
- 同上TO_INTEGER
半字节：=半字节+ 2;
- 如果int_size或nibble_size是类型，则需要
- 这些类型的运算符函数。
报告integer'IMAGE（TO_INTEGER（nibble））;
等待;
结束流程;
末端架构fum;
新增：
这是对BennyBarns在对这个问题的评论中断言的回应：我想补充一点，虽然你可以在VHDL中使用n维数组，但只有第一个可能是不受限制的。 p>
与断言相反：
实体t1是
结尾实体;
t1的结构foo是
type typeI是整数的数组（自然范围<>自然范围>）;
begin
过程是
变量sigI：typeI（0到1,0从1到1）; - 二维整数数组
begin
sigI（0,0）：= 1;
sigI（0,1）：= 2;
sigI（1,0）：= 3;
sigI（1,1）：= 4;
报告个人初始化;
报告sigI（0,0）=& integer'IMAGE（SIGI（0,0））;
报告sigI（0,1）=& integer'IMAGE（SIGI（0,1））;
报告sigI（1,0）=& integer'IMAGE（SIGI（1,0））;
报告sigI（1,1）=& integer'IMAGE（SIGI（1,1））;
sigI：=（（11,12），（13,14））;
报告初始化为汇总;
报告sigI（0,0）=& integer'IMAGE（SIGI（0,0））;
报告sigI（0,1）=& integer'IMAGE（SIGI（0,1））;
报告sigI（1,0）=& integer'IMAGE（SIGI（1,0））;
报告sigI（1,1）=& integer'IMAGE（SIGI（1,1））;
等待;
结束流程;
结束体系结构;
该语句不精确，并且在示例子类型声明中与类型声明中的延迟范围约束相关UNSIGNED包在numeric_std中。子类型指示需要由类型标记提供或明确提供的约束。它仅适用于无约束类型的子类型指示类型标记。
无约束类型的子类型声明必须提供约束，就像添加了
信号A：无符号;
作为实体foo的体系结构声明项目：
ghdl -a foo.vhdl
foo.vhdl：24：12：不允许使用无约束数组类型的信号a的声明
只是为了让事情变得有趣，接口列表可以是特殊的：
library ieee;
使用ieee.std_logic_1164.all;
使用ieee.numeric_std.all;
实体fie是
端口（
a：未签名
）;
最终实体;
fie的架构费用是
开始
EVAL：
过程（a）
开始
报告Fie：范围是&整数'IMAGE（a'LEFT）& to和
integer'IMAGE（a'RIGHT）;
结束流程;
结束架构费用;
library ieee;
使用ieee.std_logic_1164.all;
使用ieee.numeric_std.all;
实体fie_tb是
最终实体;
fie_tb的架构是
组件fie是
port（a：in unsigned）;
结束组件;
信号aa：无符号（3至7）;
begin
EUT：fie端口映射（a => aa）;
end architecture;
'规则'可以在索引约束和离散范围，IEEE Std 1076-2008 5.3.2.2，-2002 / -1993 3.2.1.1。
I was wondering is there was a way to defined a type with a size parameter in VHDL. e.g.
type count_vector(size: Natural) is unsigned (size-1 downto 0);
and then later on do something like
variable int : count_vector(32) := (others => '0');
variable nibble : count_vector(4) := (others => '0');
Essentially, is there a way to defined an "array-like" type, or is that not allowed by syntax?
I am currently trying to use generics for re-usability, but I would like to be able to take maximal advantage of generic typing (ie: Is it possible to write type-generic entities in VHDL? ).
Thanks in advance!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity foo is
generic (
constant INT_LEFT: natural := 32;
constant NIB_LEFT: natural := 4
);
-- note entity declarative items are forward looking only
-- a port declaration requires a type or subtype declared in a package
-- you can also use a package for any constants
-- a type or subtype can be declared as an entity declarative item here:
-- subtype int_size is unsigned(INT_LEFT downto 0);
-- subtype nib_size is unsigned(NIB_LEFT downto 0);
end entity;
architecture fum of foo is
-- or as an architecture declarative item here:
subtype int_size is unsigned(INT_LEFT downto 0);
subtype nib_size is unsigned(NIB_LEFT downto 0);
begin
USAGE:
process
variable int: int_size := (others => '0');
variable nibble: nib_size := (others =>'0');
begin
int := int + 3;
-- the function "+" is L: UNSIGNED, R: NATURAL
-- int_size and nibble_size are subtypes of UNSIGNED
Report integer'IMAGE(TO_INTEGER(int));
-- ditto for TO_INTEGER
nibble := nibble + 2;
-- if int_size or nibble_size were types it would require
-- operator functions for those types.
Report integer'IMAGE(TO_INTEGER(nibble));
wait;
end process;
end architecture fum;
Added:
This is in response to BennyBarns assertion in a comment on the question: "I would like to add that while you can use n-dimensional arrays in VHDL, only the first one may be unconstrained".
Contrary to the assertion:
entity t1 is
end entity;
architecture foo of t1 is
type typeI is array ( natural range <>, natural range <>) of integer;
begin
process is
variable sigI : typeI(0 to 1, 0 to 1); -- 2D integer array
begin
sigI(0,0) := 1;
sigI(0,1) := 2;
sigI(1,0) := 3;
sigI(1,1) := 4;
report "Initialized indiviually";
report "sigI(0,0) = " & integer'IMAGE(sigI(0,0));
report "sigI(0,1) = " & integer'IMAGE(sigI(0,1));
report "sigI(1,0) = " & integer'IMAGE(sigI(1,0));
report "sigI(1,1) = " & integer'IMAGE(sigI(1,1));
sigI := ((11,12),(13,14));
report "Initialized as an aggregate";
report "sigI(0,0) = " & integer'IMAGE(sigI(0,0));
report "sigI(0,1) = " & integer'IMAGE(sigI(0,1));
report "sigI(1,0) = " & integer'IMAGE(sigI(1,0));
report "sigI(1,1) = " & integer'IMAGE(sigI(1,1));
wait;
end process;
end architecture;
The statement is imprecise and relates in the example subtype declaration to the deferred range constraint in the type declaration of UNSIGNED in package numeric_std. The subtype indication requires a constraint either supplied by the type mark or explicitly. It's only valid for a subtype indication type mark that is an unconstrained type.
A subtype declaration of an unconstrained type must provide a constraint just as if you had added
signal A: unsigned;
as an architecture declarative item to fum of entity foo:
ghdl -a foo.vhdl
foo.vhdl:24:12: declaration of signal "a" with unconstrained array type "unsigned" is not allowed
And just to make things interesting things interface lists can be special:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fie is
port (
a: in unsigned
);
end entity;
architecture fee of fie is
begin
EVAL:
process (a)
begin
report "Fie:a range is " & integer'IMAGE(a'LEFT) & " to " &
integer'IMAGE(a'RIGHT) ;
end process;
end architecture fee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fie_tb is
end entity;
architecture fum of fie_tb is
component fie is
port (a: in unsigned);
end component;
signal aa: unsigned (3 to 7);
begin
EUT: fie port map (a => aa);
end architecture;
The 'rules' can be found in the LRM section on Index constraints and discrete ranges, IEEE Std 1076-2008 5.3.2.2, -2002/-1993 3.2.1.1.
这篇关于vhdl ::使用size参数创建一个类型的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
