自动SystemVerilog可变大小使用接口宽度和$ size？ [英] Automatic SystemVerilog variable size using interface width and $size?

问题描述

我正在尝试使用SystemVerilog中的标准化内存接口创建一个模块（在我的情况下是一个DSP），并希望模块中的变量根据附加接口中的总线宽度自动调整大小。我的理由：这使得代码更容易移植，允许它自动调整到任何连接的接口，而不是要求HDL编码器传递参数，告诉模块将连接到它的所有接口总线的宽度（不是这将是非常可怕的，没有参数，它似乎更干净。）

I am trying to make a module (a DSP in my case) with a standardized memory interface in SystemVerilog, and would like the variables in the module to size automatically based on the bus widths in the attached interface. My rationale: this makes the code more portable by allowing it to auto-size to any connected interface, instead of requiring an HDL coder to pass in parameters that tell the module the widths of all the interface busses that will connect to it (not that this would be terrible, it just seems cleaner without the parameters).

然而，我似乎无法使其工作。这是一个说明问题的例子;以下在Quartus II 12.1中进行综合：

I can't seem to get this to work, however. Here's an example that illustrates the problem; the following synthesizes in Quartus II 12.1:

// Top level module with some 15-bit ports

module top  ( input [14:0] data_in,
              output [14:0] data_out1, data_out2,
                            data_out3, data_out4 );

   test_interface my_interface(); // Initialize the interface
   test_module my_module(.*);     // Initialize & connect module 
endmodule

// Define a simple interface:

interface test_interface ();
   logic [8:0] my_port;
endinterface

// Define the module:

module test_module ( input [14:0] data_in,
                     test_interface my_interface,
                     output [14:0] data_out1, data_out2,
                                   data_out3, data_out4 );

   localparam width1 = $size(data_in);              // should be 15
   localparam width2 = $size(my_interface.my_port); // should be 9

   logic [width1-1:0] auto_sized1;    // gets correct size (14:0)
   logic [width2-1:0] auto_sized2;    // **PROBLEM**: gets size of 0:0!

   always_comb begin
      auto_sized1 = 5;                // ok
      auto_sized2 = 5;                // problem; value now truncated to 1 

      data_out1 = data_in + width1;      // Yields data_in + 15 (ok)
      data_out2 = data_in + width2;      // Yields data_in + 9  (ok...!) 
      data_out3 = data_in + auto_sized1; // Yields data_in + 5  (ok)
      data_out4 = data_in + auto_sized2; // Yields data_in + 1  (problem)
   end
endmodule

注意 width2 最终会得到正确的值（9） - 为了正确设置 auto_sized2 的宽度，为时已晚。我最初认为 $ size 只是在为所有变量分配了它们的宽度后才进行评估，但由于 $，这似乎不是这种情况。 size（data_in）适用于设置 auto_sized1 的宽度。

Note that width2 does eventually get the correct value (9) - just too late for it to correctly set the width of auto_sized2. I initially thought that $size was simply evaluated after all variables had been assigned their widths, but this doesn't seem to be the case either since $size(data_in) works just fine for setting the width of auto_sized1.

任意想法？同样，这对项目的成功并不重要，我现在对此非常好奇！

Any thoughts? Again, it's not critical to the project's success, I'm mostly curious at this point!

谢谢 -

推荐答案

看起来像编译器错误。我可能在接口定义中使用了一个参数。

Looks like a compiler bug. I'd probably use a parameter in the interface definition.

module top  ( input [14:0] data_in,
              output [14:0] data_out1, data_out2,
                            data_out3, data_out4 );

   test_interface #(.port_size(8)) my_interface(); // Initialize the interface
   test_module my_module(.*);     // Initialize & connect module 
endmodule

interface test_interface ();
   parameter port_size = 1;
   logic [port_size-1:0] my_port;
endinterface


module test_module ( input [14:0] data_in,
                     test_interface my_interface,
                     output [14:0] data_out1, data_out2,
                                   data_out3, data_out4 );

   localparam width1 = $size(data_in);
   localparam width2 = my_interface.port_size;
endmodule

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