基于中断的UART IO的Master [英] Master for Interrupt based UART IO

问题描述

基于中断的UART IO允许在没有CPU干预的情况下进行数据传输。现在的问题是，如果不是CPU谁控制这个？是DMA控制器还是某些外部主控制器从CPU获得对内存总线的控制。没有得到正确答案这里。如果它是DMA控制器那么什么使DMA和基于中断的传输不同

The interrupt based UART IO allows the data transfer to take place without intervention of CPU. Now the question is, if not CPU who controls this ? Is it the DMA controller or some external master who gets the control over memory bus from CPU. Didn't get a proper answer here . If it is the DMA controller then what makes DMA and interrupt based transfer different

推荐答案

没有此处获得正确答案。

如果是DMA控制器然后是什么使DMA和基于中断的传输不同

Didn't get a proper answer here .
If it is the DMA controller then what makes DMA and interrupt based transfer different

这个问题没有得到任何好的答案IMO，因为这个问题有错误的措辞。$
实际上我不理解他对中断驱动的描述，因为它没有任何意义，并不是因为我缺乏这方面的知识/经验。 br>
DMA 不能替代中断。

相反，它们是正交概念，而 这两个概念通常一起使用 。

DMA的替代方案是编程I / O，即PIO。

中断的替代方法是轮询。

That question didn't get any good answers IMO, because the question has faulty wording.
In fact I don't understand his description of "Interrupt-driven" because it makes no sense, and it's not because I lack knowledge/experience in this area.
"DMA" is not the alternative to "interrupts".
Instead they are orthogonal concepts, and both concepts are typically used together.
The alternative to DMA is programmed I/O, aka PIO.
The alternative to interrupts is polling.

DMA传输几乎总是使用完成中断（来自DMA控制器）通知CPU缓冲区传输完成。

PIO经常使用中断（来自器件）来启动每个字节/字数据传输。这有助于缓解PIO的CPU密集型特性。轮询的PIO传输否则将完全消耗CPU资源。

但是将带有中断的PIO简单地称为中断是不准确和误导性的。

DMA transfers almost alway employ a completion interrupt (from the DMA controller) to notify the CPU that a buffer transfer is complete.
PIO often uses an interrupt (from the device) to initiate each byte/word data transfer. This helps mitigate the CPU-intensive nature of PIO. A polled PIO transfer would otherwise totally consume CPU resources.
But to refer to "PIO with interrupts" as simply "interrupts" is inaccurate and misleading.

基于中断的UART IO允许在没有CPU干预的情况下进行数据传输。现在问题是，如果没有CPU控制这个？

The interrupt based UART IO allows the data transfer to take place without intervention of CPU. Now the question is, if not CPU who controls this ?

你还没有指定中断的来源;因此你的问题含糊不清。

You have not specified the source of the interrupt; therefore your question is ambiguous.

如果基于中断的应该是指来自UART的中断的PIO，那么这个问题根本没有意义，因为它是控制传输的CPU。

如果基于中断应该是指带有来自DMA控制器的中断的DMA传输，那么你正在使用这些术语在以前未在您或相关问题中使用的上下文中。

If "interrupt based" is supposed to refer to "PIO with interrupt from UART", then the question makes no sense at all, since it is the CPU that is in control of the transfer.
If "interrupt based" is supposed to refer to a DMA transfer with interrupts from the DMA controller, then you are using these terms in a context not previously used in your or the linked questions.

对于UART读取：

在DMA传输中，每个字节都从UART读取（当UART发出数据可用信号时），并由DMA控制器写入内存。必须设置DMA控制器才能执行此任务。当DMA控制器监视此传输时，CPU将执行其他（可能是不相关的）指令（例如，用于另一个进程）。

For a UART read:
In a DMA transfer, each byte is read from the UART (when the UART signals that data is available), and written to memory by the DMA controller. The DMA controller has to be setup to perform this task. While the DMA controller oversees this transfer, the CPU will be executing other (presumably unrelated) instructions (e.g. for another process).

在PIO传输中，CPU始终处于控制状态，执行从设备读取和写入存储器的指令。

In a PIO transfer the CPU is in control the entire time, executing instructions to read from the device and writing to memory.

是DMA控制器还是某些外部主控制器从CPU获取内存总线的控制权。

Is it the DMA controller or some external master who gets the control over memory bus from CPU.

内存总线由内存控制器维护。没有其他设备可以控制内存总线。

The memory bus is maintained by the memory controller. No other device gets control of the memory bus.

要实际读取或写入内存，DMA控制器会在DMA传输期间请求访问内存。 >
请注意，有些特权设备（例如总线主控器或协处理器/ GPU）也可以请求访问内存。

但CPU通常被分配了最高的内存访问优先级。

To actually read from or write to memory it is the DMA controller that requests access to memory during a DMA transfer.
Note that there are privileged devices, such as a bus master or coprocessor/GPU, that can also request access to memory.
But the CPU is typically assigned the highest priority for memory access.

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