如何在 Verilog 中设计 64 x 64 位数组乘法器? [英] How to design a 64 x 64 bit array multiplier in Verilog?

问题描述

我知道如何设计一个 4x4 数组乘法器，但如果我遵循相同的逻辑，编码就会变得乏味.

I know how to design a 4x4 array multiplier , but if I follow the same logic , the coding becomes tedious.

• 4 x 4 - 16 个部分产品
• 64 x 64 - 4096 个部分产品.

连同 8 个全加器和 4 个半加器，64 x 64 位需要多少个全加器和半加器.如何减少部分产品的数量?有什么简单的方法可以解决这个问题吗?

Along with 8 full adders and 4 half adders, How many full adders and half adders do I need for 64 x 64 bit. How do I reduce the number of Partial products? Is there any simple way to solve this ?

推荐答案

每当对重复模式进行冗长乏味的编码时，您都应该使用 generate 语句:

Whenever tediously coding a repetitive pattern you should use a generate statement instead:

module array_multiplier(a, b, y);

parameter width = 8;
input [width-1:0] a, b;
output [width-1:0] y;

wire [width*width-1:0] partials;

genvar i;
assign partials[width-1 : 0] = a[0] ? b : 0;
generate for (i = 1; i < width; i = i+1) begin:gen
    assign partials[width*(i+1)-1 : width*i] = (a[i] ? b << i : 0) +
                                   partials[width*i-1 : width*(i-1)];
end endgenerate

assign y = partials[width*width-1 : width*(width-1)];

endmodule

我已经使用以下测试平台验证了这个模块:http://svn.clifford.at/handicraft/2013/array_multiplier/array_multiplier_tb.v

I've verified this module using the following test-bench: http://svn.clifford.at/handicraft/2013/array_multiplier/array_multiplier_tb.v

由于@Debian 要求提供流水线版本 - 在这里.这次在数组部分的始终区域中使用 for 循环.

As @Debian has asked for a pipelined version - here it is. This time using a for loop in an always-region for the array part.

module array_multiplier_pipeline(clk, a, b, y);

parameter width = 8;

input clk;
input [width-1:0] a, b;
output [width-1:0] y;

reg [width-1:0] a_pipeline [0:width-2];
reg [width-1:0] b_pipeline [0:width-2];
reg [width-1:0] partials [0:width-1];
integer i;

always @(posedge clk) begin
    a_pipeline[0] <= a;
    b_pipeline[0] <= b;
    for (i = 1; i < width-1; i = i+1) begin
        a_pipeline[i] <= a_pipeline[i-1];
        b_pipeline[i] <= b_pipeline[i-1];
    end

    partials[0] <= a[0] ? b : 0;
    for (i = 1; i < width; i = i+1)
        partials[i] <= (a_pipeline[i-1][i] ? b_pipeline[i-1] << i : 0) +
                partials[i-1];
end

assign y = partials[width-1];

endmodule

请注意，对于许多综合工具，还可以在非流水线加法器之后添加(宽度)寄存器阶段，并让工具寄存器平衡传递进行流水线处理.

Note that with many synthesis tools it's also possible to just add (width) register stages after the non-pipelined adder and let the tools register balancing pass do the pipelining.

这篇关于如何在 Verilog 中设计 64 x 64 位数组乘法器?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！