仅使用半加器和全加器的带有 verilog 的 4 位乘法器 [英] Multiplier 4-bit with verilog using just half and full adders

问题描述

我正在尝试创建一个模拟 4 位乘法器而不使用乘法 (*) 的模块，只需要使用半加器和全加器，所以我成功地从某个实例编写了解决方案，这是代码:

I'm trying to create a modules that simulates 4-bit multiplier without using multiplication (*) , need just to use Half and Full adders , so I succeeded to program the solution from some instance , this is the code :

module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule

module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule

module multiply4bits(product,inp1,inp2,clock,reset,load);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;
input load;

wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;    
always @ (posedge clock )
begin
        if(reset == 1)
            begin
            // something to reset
            end
        else if (load == 1)
            begin
               product[0] = (inp1[0]&inp2[0]);
               HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
                FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
                FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
                HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
                HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
                FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
                FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
                FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
                HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
                FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
                FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
                FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10); 
            end                 
end 

endmodule

问题是我从条件 if(load == 1) 中的行中得到很多错误当我测试代码时.以下是错误:

The problem is that I get a lot of errors from the lines inside the condition if(load == 1) when I test the code. here are the errors :

第 34 行:不允许对非注册产品进行程序分配，左侧应为 reg/integer/time/genvar

Line 34: Procedural assignment to a non-register product is not permitted, left-hand side should be reg/integer/time/genvar

Line 35: Instantiation is not allowed in sequential area except checker instantiation
Line 36: Instantiation is not allowed in sequential area except checker instantiation 
Line 37: Instantiation is not allowed in sequential area except checker instantiation
.
.
Line 46: Instantiation is not allowed in sequential area except checker instantiation

如果我删除 always @ .. 并在它之外编写代码，则代码完美运行！但我必须使用时钟才能使此代码仅在 load = 1 上工作.

If I remove the always @ .. and write the code outside of it the code works perfectly ! but i must use the clock in order to get this code work just on load = 1 .

如果有人能帮助我，我将不胜感激.

If anyone can help me I'll be very thankful .

推荐答案

你也可以这样做:

module mul4(ans,aa,bb,clk,load,);

input [3:0]aa,bb;
input load,clk;
output [7:0]ans;

reg rst;

always @(posedge clk)  
    begin 
        if(load)
            rst=0; 
        else
            rst=1;
    end

multiply4bits mm(ans,aa,bb,cl,rst);

endmodule 


module multiply4bits(product,inp1,inp2,clock,reset);

output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;

wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;    

assign product[0]= (inp1[0]&inp2[0]);             
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10); 

endmodule


module HA(sout,cout,a,b);

output sout,cout;
input a,b;

assign sout = a^b;
assign cout = (a&b);

endmodule


module FA(sout,cout,a,b,cin);

output sout,cout;
input a,b,cin;

assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));

endmodule

希望它会有所帮助.

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