vhdl 4 位吠陀乘法器 [英] vhdl 4 bit vedic multiplier
问题描述
entity fourbitmult is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
p : out STD_LOGIC_VECTOR (7 downto 0));
end fourbitmult;
architecture Behavioral of fourbitmult is
component twobitmult
port(a,b:in std_logic_vector(1 downto 0);
p:out std_logic_vector (3 downto 0));
end component;
component rca
port(a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
carry:out std_logic;
cin:in std_logic='0'
);
end component;
component halfadder
port(a,b:in std_logic;
s,c:out std_logic);
end component;
signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22: std_logic;
begin
m1:twobitmult port map(a(0),a(1),b(0),b(1),p(0),p(1),c1,c2);
m2:twobitmult port map(a(2),a(3),b(0),b(1),c15,c16,c17,c18);
m3:twobitmult port map(a(0),a(1),b(2),b(3),c19,c20,c21,c22);
m4:twobitmult port map(a(2),a(3),b(2),b(3),c7,c8,c9,c10);
r1:rca port map(c15,c16,c17,c18,c19,c20,c21,c22,c3,c4,c5,c6,c12);
r2:rca port map(c1,c2,c7,c8,c3,c4,c5,c6,p(2),p(3),p(4),p(5),c11);
c13<=c11 or c12;
h1:halfadder port map(c13,c9,p(6),c14);
h2:halfadder port map(c14,c10,p(7));
end Behavioral;
我为 4 位吠陀乘法器编写了 VHDL 代码.我收到如下错误:
I wrote a VHDL code for the 4 bit vedic multiplier. I am getting an error as:
Line 45. parse error, unexpected EQ, expecting SEMICOLON or CLOSEPAR"..
语法完全正确，我不明白为什么会出错.可能有什么问题?
The syntax is perfectly right, I don't understand why it's an error. What could be wrong?
推荐答案
语法完全正确
不完全.
cin:in std_logic='0'
应该
cin: in std_logic := '0'
------------------^
您还缺少开头的上下文子句:
You're also missing the context clause at the beginning:
library ieee;
use ieee.std_logic_1164.all;
您显然已经删除了该内容和一些标题注释，但没有指明哪一行是第 45 行(这是上面摘录的行).您的示例不是一个最小、完整和可验证的示例.
You've deleted that and some header comments apparently, without indicating which line was line 45 (and it's the line excerpted above). Your example isn't quite a Minimal, Complete, and Verifiable example.
当您始终如一地使用空格和缩进时，很容易出现语法错误.
Syntax errors tend to show up easily when you use white space and indentation consistently and well.
愿意就语义提出主张吗?
在港口地图中发现的实际数比形式数更多"的附录
正如您发现的那样，您也有语义错误以及上述语法错误.虽然您没有更新您的问题，但这些错误也可以在这里解释.
As you've discovered you also have semantic errors as well as the above syntax error. While you didn't update your question, those errors can be explained here too.
原始第 54 - 59 行的在端口映射中找到的实际值比在形式上更多"是因为您在端口映射关联中的端口数与 twobitmult<的组件声明中声明的端口数不同/code> 和 rca 实例.
The " More actuals found than formals in port map" for original lines 54 - 59 are because you don't have the same number of ports in the port map associations as are declared in the component declarations for twobitmult and rca instances.
您可以通过使用命名关联来解决这些问题，该关联允许您使用与实际数组基本元素类型关联的形式数组端口元素.(允许比端口数量更多的关联列表条目).
You can cure these by using named association which allows you to use a formal's array port elements associated with an array base element type actual. (Allowing more association list entries than the number of ports).
请注意，您在 rca 组件声明中似乎有错误，显示的端口映射关联比扩展数组类型所能提供的要多.
Note that you appear to have an error with the rca component declaration, there are more port map associations shown than are possible by expanding array types.
看来 carry 旨在成为数组类型(并且以下已被注释以反映这一点).
It appears carry is intended to be an array type (and the following has been annotated to reflect that).
另请注意，组件中的数组类型是使用降序的端口元素索引声明的，并将它们与实体 fourbitmult 数组类型端口的升序元素相关联.
Also note that your array types in your components are declared with port element indexes in a descending order and you associate them with ascending order elements of entity fourbitmult array type ports.
如果您能够使用与声明的范围方向相同的实际值切片，关联列表条目可以简化为 a =>;a(1 downto 0), 例如.这同样适用于您可以连接切片实际值的其他地方.
Should you be able to use slices of the actuals with the same range direction as they are declared the association list entry could be simplified as a => a(1 downto 0), for example. The same holds true for other places you can connect slice actuals.
因此通过使用形式元素使端口数匹配:
So making the number of ports match by using formal elements:
library ieee;
use ieee.std_logic_1164.all;
entity fourbitmult is
port (
a,b: in std_logic_vector (3 downto 0);
p: out std_logic_vector (7 downto 0));
end fourbitmult;
architecture behavioral of fourbitmult is
component twobitmult
port (
a,b: in std_logic_vector (1 downto 0);
p: out std_logic_vector (3 downto 0)
);
end component;
component rca
port (
a,b: in std_logic_vector (3 downto 0);
s: out std_logic_vector (3 downto 0);
carry: out std_logic_vector (3 downto 0); -- std_logic;
cin: in std_logic := '0' -- formerly line 45
);
end component;
component halfadder
port (
a,b: in std_logic;
s,c: out std_logic
);
end component;
signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,
c13,c14,c15,c16,c17,c18,c19,c20,c21,c22: std_logic;
begin
m1:
twobitmult
port map (
-- a(0),a(1),b(0),b(1),p(0),p(1),c1,c2
a(1) => a(0),
a(0) => a(1),
b(1) => b(0),
b(0) => b(1),
p(3) => p(0),
p(2) => p(1),
p(1) => c1,
p(0) => c2
);
m2:
twobitmult
port map (
-- a(2),a(3),b(0),b(1),c15,c16,c17,c18
a(1) => a(2),
a(0) => a(3),
b(1) => b(0),
b(0) => b(1),
p(3) => c15,
p(2) => c16,
p(1) => c17,
p(0) => c18
);
m3:
twobitmult
port map (
-- a(0),a(1),b(2),b(3),c19,c20,c21,c22
a(1) => a(0),
a(0) => a(1),
b(1) => b(2),
b(0) => b(3),
p(3) => c19,
p(2) => c20,
p(1) => c21,
p(0) => c22
);
m4:
twobitmult
port map (
-- a(2),a(3),b(2),b(3),c7,c8,c9,c10
a(1) => a(2),
a(0) => a(3),
b(1) => b(2),
b(0) => b(3),
p(3) => c7,
p(2) => c8,
p(1) => c9,
p(0) => c10
);
r1:
rca
port map (
--c15,c16,c17,c18,c19,c20,c21,c22,c3,c4,c5,c6,c12
a(3) => c15,
a(2) => c16,
a(1) => c17,
a(0) => c18,
b(3) => c19,
b(2) => c20,
b(1) => c21,
b(0) => c22,
carry(3) => c3,
carry(2) => c4,
carry(1) => c5,
carry(0) => c6,
cin => c12
);
r2:
rca
port map (
-- c1,c2,c7,c8,c3,c4,c5,c6,p(2),p(3),p(4),p(5),c11
a(3) => c1,
a(2) => c2,
a(1) => c7,
a(0) => c8,
b(3) => c3,
b(2) => c4,
b(1) => c5,
b(0) => c6,
carry(3) => p(2),
carry(2) => p(3),
carry(1) => p(4),
carry(0) => p(5),
cin => c11
);
c13 <= c11 or c12;
h1:
halfadder
port map (
c13,c9,p(6),c14
);
h2:
halfadder
port map (
c14,c10,p(7)
);
end behavioral;
此分析，但如果没有声明组件的实体/架构对，则无法详细说明，也无法验证功能.
This analyzes, but without the entity/architecture pairs for the declared components can't be elaborated, nor the functionality verified.
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