在 VHDL 中的实体内声明数组 [英] Declaring an array within an entity in VHDL

问题描述

我正在尝试为小型 CPU 设计制作一个缓冲区来保存 16 条 16 位宽的指令.

I'm trying to make a buffer to hold 16, 16-bit wide instructions for a small CPU design.

我需要一种方法将指令从我的测试平台加载到缓冲区中.所以我想使用 std_logic_vectors 数组来完成这个.但是，我收到一个语法错误，我不知道为什么(或者我是否被允许在 VHDL 中这样做).

I need a way to load instructions into the buffer from my testbench. So I wanted to use an array of std_logic_vectors to accomplish this. However, I am getting a syntax error and I'm not sure why (or if I'm allowed to do this in VHDL for that matter).

语法错误在我声明instructions

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;




entity instruction_buffer is
    port
    (
    reset               : in std_logic;
    instructions        : in array(0 to 15) of std_logic_vector(15 downto 0);
    instruction_address : in  std_logic_vector(3 downto  0);
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

我也尝试过这样做，但随后在实体端口映射中出现语法错误，告诉我 std_logic_vector 是未知类型.我发誓，VHDL 的语法错误没有 C 那么有意义 哈哈

I've tried doing like this as well, but then I get syntax errors in my entity port mapping telling me that std_logic_vector is an unknown type. I swear, VHDL's syntax errors are less meaningful than C haha

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

package instructionBuffer is
    type instructionBuffer is array(0 to 15) of std_logic_vector (15 downto 0);
end package instructionBuffer;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(3 downto  0);
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

推荐答案

无需拆分成两个文件，只需将所有代码放在一个文件中即可.您还可以在包中使用泛型来实现可扩展性:

There is no need to split into two files, simply put all code into one file. You can also use generics inside your package for scalability:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package instruction_buffer_type is
constant INSTRUCTION_BUFFER_ADDRESS : integer := 4;  --bits wide
constant INSTRUCTION_BUFFER_DATA    : integer := 16; --bits wide
type instructionBuffer is array(0 to 2**INSTRUCTION_BUFFER_ADDRESS -1) of std_logic_vector (INSTRUCTION_BUFFER_DATA -1 downto 0);
end package instruction_buffer_type;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.instruction_buffer_type.all;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(INSTRUCTION_BUFFER_ADDRESS-1 downto  0);
    instructions        : in instructionBuffer;
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(INSTRUCTION_BUFFER_DATA-1 downto 0)
    );
end instruction_buffer;

这篇关于在 VHDL 中的实体内声明数组的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！