VHDL:ieee std_logic 库中的真值表 [英] VHDL: truth table in ieee std_logic library

问题描述

我研究了 IEEE 如何定义其库.当我打开 stdlogic library 时，我看到了一些定义为常量的真值表.我不知道真值表是如何运作的.请解释如何使用真值表返回结果.这是我发现的AND"门:

I looked into how IEEE defines its libraries. When I opened up stdlogic library, I saw a few truth tables that are defined as constant. I have no idea how the truth tables function. Please explain how the result is returned using truth table. Here is what I found for "AND" gate:

TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;

-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
--      ----------------------------------------------------
--      |  U    X    0    1    Z    W    L    H    -         |   |  
--      ----------------------------------------------------
        ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ),  -- | U |
        ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),  -- | X |
        ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ),  -- | 0 |
        ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | 1 |
        ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),  -- | Z |
        ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),  -- | W |
        ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ),  -- | L |
        ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | H |
        ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )   -- | - |
);

FUNCTION "and"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
    RETURN (and_table(l, r));
END "and";

UX01"定义为

SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO 'Z';

我不知道如何使用关键字已解决".resolved"定义为库中的函数

I have no idea how the key word "resolved" is used. "resolved" is defined as a function in the library

FUNCTION resolved (s: std_ulogic_vector) RETURN std_ulogic;

我用谷歌搜索了一段时间真值表的功能，但没有找到解释.请解释该表如何评估输入.非常感谢

I googled how the truth table functions for a while, but no luck to find a explanation. Please explain how the table evaluates the inputs. Thanks a lot

推荐答案

充满声明的 AND 表是一个二维数组，由 std_ulogic(枚举)值索引.AND 函数有一个左右参数(l 和 r)，用于在表中索引结果.

The AND table replete with declarations you show is a two dimensional array, indexed by std_ulogic (enumerated) values. An AND function has a left and right argument (l and r), use to index a result in the table.

该表显示为二维数组以使其用户可读，列注释枚举值索引和行注释枚举值索引的交集表示逻辑与运算的结果.

The table is shown as a 2D array to make it user readable, the intersection of a column comment enumerated value index and row comment enumerated value index indicating the result of a logical AND operation.

解析函数有点复杂，需要从标准或各种解释性文本中进行高级阅读.

Resolution functions are a bit more complex and involve advanced reading either from the standard or various explanatory texts.

解析函数用于在一个信号上解析"多个驱动程序.各种驱动程序值被组织为一个向量，其长度等于驱动程序的数量，在第一个驱动程序值根据默认驱动程序解析"之后(在这种情况下，请参阅 std_logic_1164 的包体，result 是 'Z')，每个连续的驱动程序都是通过对累积的 result 进行解析表查找来解决的.

A resolution function is used to 'resolve' multiple drivers on a signal. The various driver values are organized as a vector with the length equal to the number of drivers, where after the first driver value being 'resolved' against a default driver (in this case see the package body of std_logic_1164, the default value for result is 'Z'), each successive driver is resolved by resolution table look up against the accumulated result.

目的是确定具有多个驱动器的信号的已解析"信号值，在这种情况下使用作为 IEEE 标准(IEEE Std 1164，现在是 VHDL 标准的一部分)采用的 MVL9(具有 9 级的多级逻辑). 这是语言的一部分(而不是像 Guy Sirton 所说的那样纯粹是电气工程问题).

The purpose is to determine the 'resolved' signal value of a signal having multiple drivers, in this case using the MVL9 (multi level logic with 9 levels) adopted as an IEEE Standard (IEEE Std 1164, now part of VHDL standard. It's part of the language (and not as Guy Sirton indicates solely an electrical engineering issue).

设置分辨率是在细化过程中进行的，它是一种模拟功能.

Setting up resolution occurs during elaboration it's a function of simulation.

驱动相同信号的任何两个并发语句都需要解析.即使只有一个驱动程序(针对默认的Z")也会出现解决方案.如果您不使用已解析的类型，您将收到一条错误消息.如果您使用已解析的类型，您将获得一个解析值，并且在您可能不应该这样做时，将无法防止将多个驱动程序连接到同一信号.

Any two concurrent statements driving the same signal require resolution. Resolution occurs even with only one driver (against that default 'Z'). If you don't use resolved types you'll get an error message. If you use resolved types you'll get a resolution value and won't be protected against connecting multiple drivers to the same signal when perhaps you shouldn't be doing so.

附录

还有一个问题.为了浏览二维数组，我认为我们使用数组索引.Like (1,2) = row 1, column 2. 怎么用and_table(U,1)匹配第 1 行、第 4 列或第 1 列第 4 行?– 潘红 1 小时前

One more question. To navigate through a 2D array, I thought we use array index. Like (1,2) = row 1, column 2. use how does and_table(U,1) matches up Row 1, Column 4 or Column 1 row 4? – Hong Pan 1 hour ago

未针对再问一个问题"设置问答格式.

The question and answer format isn't set up for 'One more question'.

索引是 std_ulogic 类型，而不是数字类型.枚举类型具有可以表示为数字类型的位置值.对于 std_ulogic 枚举值，第一个值是U"，接下来是X"，...到-".要查找 std_ulogic 位置值，您可以使用 'POS 属性，其中 std_ulogic'POS(l) 将返回 l 的索引位置值.您可以使用 'VAL 属性将表示位置值的通用整数转换为 std_ulogic 值.

The indexes are type std_ulogic, not numerical types. An enumerated type has a positional value that can be expressed as a numerical type. For std_ulogic enumeration values, the first value is 'U' the next is 'X',... on to '-'. To find a std_ulogic positional value you could use the 'POS attribute where std_ulogic'POS(l) will return an index position value for l. You can convert a universal integer number representing a positional value to a std_ulogic value by using the 'VAL attribute.

索引值 l 和 r 按照惯例用于表示左和右 操作数 到预定义的二元运算符.l AND r 提供了 l 和 r 两个索引.

The index values l and r are used by convention to signify left and right operands to predefined binary operators. l AND r provides the two indexes as l and r.

FUNCTION "and"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
    RETURN (and_table(l, r));
END "and";

您不能使用接口列表指定预定义的运算符 - AND(l,r).l 是第二个维度，指定行，而 r 指定列.在这些情况下并不重要，表的工作方式相同，切换两个索引.

You're not allowed to specify a predefined operator with an interface list - AND(l,r). l is the second dimension, specifying rows while r specifies columns. And it doesn't matter in these cases, the tables work the same switching the two indexes.

请注意，返回值是 std_ulogic 的子类型 (UX01)，并且在表中仅找到这四个值.

Note the return value is a subtype (UX01) of std_ulogic and only those four values are found in the table.

知识渊博的 VHDL 用户可以从您在示例中提供的信息中辨别出所有这些.它说明需要关于语言或访问标准(IEEE Std 1076-2008)的良好文本，其中可以找到所有答案.

And all of this can be discerned by the knowledgeable VHDL user from the the information you provided in your example. It speaks to the need for a a good text on the language or access to the standard (IEEE Std 1076-2008), wherein all answers can be found.

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