L1 缓存命中与 x86 上注册的周期/成本? [英] Cycles/cost for L1 Cache hit vs. Register on x86?

问题描述

我记得在我的架构类中假设 L1 缓存命中是 1 个周期(即与寄存器访问时间相同)，但在现代 x86 处理器上实际上是这样吗?

I remember assuming that an L1 cache hit is 1 cycle (i.e. identical to register access time) in my architecture class, but is that actually true on modern x86 processors?

L1 缓存命中需要多少个周期?与注册访问权限相比如何?

How many cycles does an L1 cache hit take? How does it compare to register access?

推荐答案

这里有一篇关于这个主题的精彩文章:

Here's a great article on the subject:

http://arstechnica.com/gadgets/reviews/2002/07/caching.ars/1

回答您的问题 - 是的，缓存命中的成本与寄存器访问的成本大致相同.当然，缓存未命中的代价是相当大的 ;)

To answer your question - yes, a cache hit has approximately the same cost as a register access. And of course a cache miss is quite costly ;)

附注:

具体情况会有所不同，但此链接有一些不错的大致数据:

The specifics will vary, but this link has some good ballpark figures:

访问各种缓存和主内存的大概成本?

Core i7 Xeon 5500 Series Data Source Latency (approximate)
L1 CACHE hit, ~4 cycles
L2 CACHE hit, ~10 cycles
L3 CACHE hit, line unshared ~40 cycles
L3 CACHE hit, shared line in another core ~65 cycles
L3 CACHE hit, modified in another core ~75 cycles remote
L3 CACHE ~100-300 cycles
Local DRAM ~30 ns (~120 cycles)
Remote DRAM ~100 ns 

PPS:

这些数字代表更旧、更慢的 CPU，但比率基本保持不变:

These figures represent much older, slower CPUs, but the ratios basically hold:

http://arstechnica.com/gadgets/reviews/2002/07/caching.ars/2

Level                    Access Time  Typical Size  Technology    Managed By
-----                    -----------  ------------  ---------     -----------
Registers                1-3 ns       ?1 KB          Custom CMOS  Compiler
Level 1 Cache (on-chip)  2-8 ns       8 KB-128 KB    SRAM         Hardware
Level 2 Cache (off-chip) 5-12 ns      0.5 MB - 8 MB  SRAM         Hardware
Main Memory              10-60 ns     64 MB - 1 GB   DRAM         Operating System
Hard Disk                3M - 10M ns  20 - 100 GB    Magnetic     Operating System/User

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