如何强制GNU make重新编译在具有不同FLAGS的两个目标中使用的同一目标文件 [英] How to force GNU make to recompile the same object file used in two targets with different FLAGS

问题描述

假设您有一个makefile，其中包含两个目标，如下所示:

Suppose you have have a makefile containing two targets as in the following:

# targetA
X86CPPTARGET += targetA
targetA,SRCS = FILEA.cpp  FILEB.cpp commonFile.cpp
targetA.so,DEPSOL = libUsedByCommon1.cpp
targetA,CPPFLAGS += -Ifakeinclude -std=c++11

# tartargetBgetA
X86CPPTARGET += targetB
targetB,SRCS = FILEC.cpp  FILED.cpp commonFile.cpp
targetA.so,DEPSOL = libUsedByCommon2.cpp
targetB,CPPFLAGS += -std=c++11

targetA和targetB共享一个文件，即commonFile.cpp，其中包含许多#include d头. commonFile.o仅由GNU make创建一次，并且在targetB的编译期间可以重复使用.

targetA and targetB share a file, namely, commonFile.cpp which contains a number of #included headers. commonFile.o is created only once by GNU make and reused during the compilation of targetB.

targetA中的CPPFLAGS使编译器使用一个include，该include包含更多符号，而默认include目录中的符号更多. libUsedByCommon2不会导出fakeinclude目录的标头中包含的所有其他符号，并且在链接时，这会导致undefined reference.

The CPPFLAGS present in targetA makes the compiler use an include that contains more symbols that the one that is in the default include directory. libUsedByCommon2 does not export all the additional symbols that are contained in the header in the fakeinclude directory and at link time, this results in undefined reference.

我目前使用的解决方法是创建一个指向commonFile.cpp的符号链接，并在我的makefile中仅在一个目标中使用它.

The workaround I am usingat the moment is to create a symbolic link to commonFile.cpp and use that in my makefile in only one of the target.

# targetA
X86CPPTARGET += targetA
targetA,SRCS = FILEA.cpp  FILEB.cpp commonFile.cpp
targetA.so,DEPSOL = libUsedByCommon1.cpp
targetA,CPPFLAGS += -Ifakeinclude -std=c++11

# tartargetBgetA
X86CPPTARGET += targetB
targetB,SRCS = FILEC.cpp  FILED.cpp **commonFile_symbolic_link.cpp**
targetA.so,DEPSOL = libUsedByCommon2.cpp
targetB,CPPFLAGS += -std=c++11

有没有更清洁的解决方案来解决这个问题? 使用不同的包含路径时，是否有一种方法可以强制GNU make重新编译commonFile.cpp?

Is there a cleaner solution to this problem? Is there a way to force GNU make to recompile commonFile.cpp when a different include path is being used?

推荐答案

您可以使用两个不同的构建命令来创建两个依赖于同一C文件的新目标，例如以下示例...

You could create two new targets who are dependent on the same C file with different build commands like the following example...

commonFileA.o: commonFile.cpp
    $(CC) -o $@ $^ -FlagsA

commonFileB.o: commonFile.cpp
    $(CC) -o $@ $^ -FlagsB

然后您可以使用"commonFileA.o"作为依赖项，以在版本中链接这些特定标志等.

You can then use "commonFileA.o" as a dependency to link in the version with those particular flags etc...

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