您将如何在Verilog或VHDL中实现这种数字逻辑? [英] How would you implement this digital logic in Verilog or VHDL?
问题描述
我发布了 answer 来另一个stackoverflow问题,该问题需要一些数字逻辑将在Verilog或VHDL中实现,以便可以将其编程到FPGA中.
I posted an answer to another stackoverflow question which requires some digital logic to be implemented in Verilog or VHDL so that it can be programmed into an FPGA.
如何用Verilog,VHDL或任何其他硬件描述语言实现以下逻辑图?
带编号的框表示字段中的位.每个字段都有 K 位,并且 current 和 mask 的位将由计算机系统(使用锁存寄存器或等效寄存器)提供. next 中的位将被读回到同一计算机系统中.
The numbered boxes represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a computer system (using a latched register or equivalent). The bits in next will be read back into that same computer system.
替代文字http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7 .jpg
另请参见:此stackoverflow问题
推荐答案
是这样的吗?
module scheduler
#( parameter K = 10 )
(
input wire [K:1] current,
input wire [K:1] mask,
output reg [K:1] next
);
reg [K:1] a;
reg [K:1] b;
//'[i+1]' busses that wrap.
// eg, for a 4-bit bus...
// a[i]: a[4],a[3],a[2],a[1] (obviously...)
// a_wrap[i]: a[1],a[4],a[3],a[2]
wire [K:1] mask_wrap = { mask[1],mask[K:2] };
wire [K:1] a_wrap = { a[1], a[K:2] };
wire [K:1] current_wrap = { current[1], current[K:2] };
integer i;
always @( * ) begin
for( i=1; i<=K; i=i+1 ) begin
a[i] = ~current_wrap[i] && b[i];
b[i] = a_wrap[i] || mask_wrap[i];
next[i] = ~a[i] && mask_wrap[i];
end
end
endmodule
(免责声明:倾斜但未模拟)
(Disclaimer: linted but not simulated)
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