Verilog中的if语句和辅助线 [英] If statement and assiging wires in Verilog

问题描述

Verilog的新手，它试图弄清楚基于组合逻辑的辅助导线的基础.

New to Verilog and trying to figure out the basics of assiging wires based on combination logic.

我有:

wire val;
wire x;
wire a;
wire b;

always @*
begin

if(val == 00)
 I want to assign x = a
if(val == 01)
 I want to assign x = b

end

其中a和b是具有值的导线-x是进入寄存器的导线.

where a and b are wires with values - and x is a wire going into a register.

如果可以的话，请向我指出我需要更改的正确方向，将不胜感激.

If you can please point me in the right direction to what I need to change, it would be much appreciated.

谢谢.

推荐答案

首先要问的是:您是否要使用这些导线作为输入?还是使用这些作为连接? 第二件事:您想要一个可综合的代码吗? 而且您不能在Always块内分配电线，必须使用reg

First thing to ask is: are you trying to use those wires as inputs? Or are you using those as connections? Second thing: Do you want a synthesizable code? And you cant assign wires inside an always block, you have to use reg

因此，意见是:

//**************************************************************************************
module(a, b, out); //You have to define an interface, and all Verilog modules starts with module 
input val[1:0]; //you have to use [] in order to indicate the length. In this case 2 bits, since you want to ask for 00;
input a;
input b;
output out;

reg x;

always @* //NOTE: You are describing combo logic, since there is no clock signal
begin

      if(val == 2'b00)
        x = a;
      else if(val == 2'b01)
        x = b;
      else 
        x = 0; //If you are describing combo logic, you have to cover ALL val cases, in                     order to evade latches

end

assign out = x; //This is how you assign values in Verilog

endmodule

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