Verilog 中的断言语句 [英] Assert statement in Verilog

问题描述

我对 Verilog 完全陌生，请耐心等待.

I'm completely new to Verilog, so bear with me.

我想知道 Verilog 中是否有 assert 语句.在我的测试平台中，我希望能够断言模块的输出等于某些值.

I'm wondering if there is an assert statement in Verilog. In my testbench, I want to be able to assert that the outputs of modules are equal to certain values.

例如

mymodule m(in, out);
assert(out == 1'b1);

谷歌搜索给了我一个几个链接，但它们要么太复杂，要么似乎没有成为我想要的.

Googling gave me a few links, but they were either too complex or didn't seem to be what I wanted.

推荐答案

有一个用于断言的开源库，名为 OVL.然而，它相当沉重.我从那里得到的一个技巧是创建一个模块来做断言.

There is an open source library for assertions called OVL. However, it's pretty heavy. One trick I nicked from there is creating a module to do assertions.

module assert(input clk, input test);
    always @(posedge clk)
    begin
        if (test !== 1)
        begin
            $display("ASSERTION FAILED in %m");
            $finish;
        end
    end
endmodule

现在，任何时候你想检查一个信号，你所要做的就是在你的模块中实例化一个断言，就像这样:

Now, any time you want to check a signal, all you have to do is instantiate an assertion in your module, like this:

module my_cool_module(input clk, ...);

     ...

     assert a0(.clk(clk), .test(some_signal && some_other_signal));

     ...

endmodule

当断言失败时，您将收到如下消息:

When the assertion fails, you'll get a message like this:

ASSERTION FAILED in my_cool_module.a0

显示语句中的 %m 将显示违规断言的整个层次结构，当您在大型项目中拥有大量这些时，这很方便.

The %m in the display statement will show the entire hierarchy to the offending assertion, which is handy when you have a lot of these in a larger project.

你可能想知道我为什么要检查时钟的边缘.这很微妙，但很重要.如果上述表达式中的 some_signal 和 some_other_signal 被分配到不同的 always 块中，则表达式可能会在短时间内为 false，具体取决于您的 Verilog 模拟器调度块的顺序(即使逻辑完全有效).这会给你一个假阴性.

You may wonder why I check on the edge of the clock. This is subtle, but important. If some_signal and some_other_signal in the expression above were assigned in different always blocks, it's possible the expression could be false for a brief period of time depending on the order that your Verilog simulator schedules the blocks (even though the logic was entirely valid). This would give you a false negative.

上面要注意的另一件事是我使用了 !==，如果测试值为 X 或 Z，这将导致断言失败.如果使用正常的 !=，它可能会在某些情况下默默地给出误报案例.

The other thing to note above is that I use !==, which will cause the assertion to fail if the test value is X or Z. If it used the normal !=, it could silently give a false positive in some cases.

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