#delay对于Verilog非阻塞语句如何工作？ [英] How does #delay work for verilog non blocking statements?

问题描述

第二个$ display语句中将为A和B打印什么？

What will be printed for A and B in the second $display statement?

module blocking;
reg[0:7] A, B;
initial begin
   A = 3;
   #1 A = A + 1; 
   B = A + 1;
  $display("Blocking: A= %d B= %d", A, B ); // A = 4, B = 5
   A = 3;
   #1 A <= A + 1;
   B <= A + 1;
   #1 $display("Non-blocking: A= %d B= %d", A, B ); // A = ?, B = ?
end
endmodule

关于verilog中的事件调度如何工作的任何指针延迟和非阻塞性声明将非常有帮助。谢谢。

Any pointers on how event scheduling in verilog works with respect to delays and non blocking statements will be really helpful. Thanks.

推荐答案

因为在第二个$ display语句之前有＃1，它将在A和B被执行后的下一个循环中执行安顿下来。

because you have #1 before the second $display statement, it will be executed in the next cycle after A and B are settled.

假设我们处于循环＃1。

Say we are at cycle #1.

A = 3; // at #1
#1 // (does not matter) --> #2
A <= A + 1; // #2 will do A + 1 and wait till the end of the cycle 
B <= A + 1; // #2 same as above
// at the end of the cycle #2 (nba scheduling bucket) before switching to #3 
//    A and B will be assigned '4'
#1 // --> #3
// new values of A and B are available here (4)
$display("Non-blocking: A= %d B= %d", A, B );

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