具有内部分配延迟的阻塞语句和非阻塞语句之间的差异 [英] difference between blocking and non blocking statements with intra-assignment delay

问题描述

以下两个Verilog代码片段之间有什么区别?

What is the difference between the following 2 snippets of verilog code?

1)

always@(in)
  out = #5 in;

AND

2)

 always@(in)
   out <= #5 in;

考虑到在always块中没有其他行，输出会不会有任何差异? 问题与幻灯片16有关(请参阅o5和o6输出) http://www.sutherland-hdl.com/papers/1996-CUG -presentation_nonblocking_assigns.pdf

Considering no other lines are present in the always block, can there be any difference in output? question is in reference to slide 16 (see o5 and o6 outputs) http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

推荐答案

out = #5 in;阻止5个时间单位的下一个操作.在经过5个时间单位之前，它将阻止监视下一个@(in).如果您在作业前后添加$display语句，则会看到已经过去了5个时间单位.

out = #5 in; blocks the next operation for 5 time units. It will prevent the monitoring of the next @(in) until the the 5 time units have passed. If you add a $display statement just before and after the assignment you will see 5 time units has passed.

always @(in) begin
    $display("enter @ %0t",$realtime);
    out = #5 in;
    $display("exit @ %0t",$realtime);
end
/*******************
 * Example output:
 * enter @ time 10
 * exit @ time 15
 *******************/

out <= #5 in;计划将来发生的5个时间单位的分配，并允许下一个操作开始而无需等待分配完成.

out <= #5 in; schedules the assignment of occur 5 time units in the future and allows the next operation to begin without waiting for assignment to complete.

always @(in) begin
    $display("enter @ %0t",$realtime);
    out <= #5 in;
    $display("exit @ %0t",$realtime);
end
/*******************
 * Example output:
 * enter @ time 10
 * exit @ time 10
 *******************/

在EDA游乐场的工作示例: http://www.edaplayground.com/s/6/114

Working example at the EDA Playground: http://www.edaplayground.com/s/6/114

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