非阻塞赋值的 Verilog 序列 [英] Verilog sequence of non blocking assignments

问题描述

说出以下代码段(同一块):

Say the following code section (same block):

A <= 1
A <= 2

变量 A 总是被赋值为 2 吗?还是会出现竞争条件并分配 1 或 2 ?

Will variable A always be assigned 2? or will there be a race condition and 1 or 2 will be assigned ?

我对非阻塞赋值的理解是，由硬件在未来分配变量 A，因此它可能是一个随机结果.然而，这是不直观的.模拟显示 2 总是被分配，但我想知道这是否肯定硬件综合的情况.

My understanding of non blocking assignment is that it is up to the hardware to assign the variable A at a future time so it could be a random result. However, this is non intuitive. Simulations show that 2 always get assigned, but I would like to know if this is definitely the case for hardware synthesis.

推荐答案

A 在模拟中为 2，最后定义的值生效.如果它们不在同一个块中，则可能存在竞争条件，具体取决于模拟器调度程序在模拟中最后定义哪个.

A would be 2 in simulation, the last defined value takes effect. If they are not in the same block then there could be a race condition depending on the simulator scheduler as to which was defined last in simulation.

我已经看到这种技术使用了很多，并且在合成后从未见过任何意想不到的结果.

I have seen this technique used quite a lot and never seen any unexpected results after synthesis.

来自 Verilog IEEE 1364-2005 第 11.4.1 节确定性

From Verilog IEEE 1364-2005 Section 11.4.1 Determinism

begin-end 块中的语句应按照它们在该 begin-end 块中出现的顺序执行.可以暂停特定开始-结束块中语句的执行，以支持模型中的其他进程；但是，在任何情况下，begin-end 块中的语句都不应以它们在源代码中出现的顺序以外的任何顺序执行.

Statements within a begin-end block shall be executed in the order in which they appear in that begin-end block. Execution of statements in a particular begin-end block can be suspended in favor of other processes in the model; however, in no case shall the statements in a begin-end block be executed in any order other than that in which they appear in the source.

这也在 SystemVerilog-IEEE1800 2012 中作为第 4.6 节确定性

This is also in SystemVerilog-IEEE1800 2012 as section 4.6 Determinism

使用它可能是一个 FSM，它稀疏地定义了它的输出:

Usage of this might be a FSM which sparsely defines its outputs:

always @(posedge clk) begin
  out_one <= 1'b0;
  out_two <= 1'b0;
  out_thr <= 1'b0;
  case (state)
    2'd1 : out_one <= 1'b1;
    2'd2 : out_two <= 1'b1;
    2'd3 : out_thr <= 1'b1;
  endcase
end

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