Verilog 中的 For 循环 [英] For-loop in Verilog

问题描述

我是 Verilog 的新手，所以我在使用 if 时遇到了一些问题

I am new to Verilog so I am having some problems working with if

基本上我有一个 5 位数字，并且想要拆分它以便我可以有一个 2 位数的十进制数.为此，我有这段代码

Basically I have a 5 bit number, and a want to split it so I can have a 2 digits decimal number. For doing so I have this piece of code

reg [4:0] position, aux;
reg [3:0] display1, display2;
reg [2:0] secondDigit;

always @(negedge iKEY[1] or negedge iKEY[2]) begin
    aux = position;

    for(secondDigit = 2'b0; aux >= 5'b01010; secondDigit = secondDigit + 2'b01)
        aux = aux - 5'b01010;

    assign display1 = aux[3:0];
    assign display2 = {2'b0, secondDigit};

end

问题是我收到了

loop with non-constant loop condition must terminate within 250 iterations

我也试过用 for 循环代替这个 while，但一直得到同样的错误

I also tried substituting the for loop for this while, but keep getting the same error

aux = position;
secondDigit = 2'b0;
while(aux > 5'b01010) begin
    aux = aux - 5'b01010;
    secondDigit = secondDigit + 2'b01;
end

有人可以帮我吗?谢谢

推荐答案

如果将逻辑分成两个 always 块会更容易.一种用于组合逻辑，一种用于同步逻辑.在组合逻辑中应该看起来像下面这样.请注意，for 循环可以分解为三个连续的 if 语句.

It would be easier if you divided your logic up into a two always blocks. One for combination logic and one for synchronous logic. In the combination logic should looks something like below. Note that the for-loop can unravel to three sequential if-statements.

integer index;
always @* begin // combination logic
  aux = position;
  secondDigit = 2'b00;
  for(index = 0; index < 3; index = index + 1) begin
    if(firstDigit >= 5'b0_1010) begin
      aux = aux- 5'b0_1010;
      secondDigit = secondDigit + 1'b1;
    end
  end
end

正如 Morgan 所说，你不应该使用 @(negedge iKEY[1] or negedge iKEY[2])，因为它会产生奇怪的综合结果.看起来你打算失败.我会推荐以下内容:

As Morgan mentioned, you should not use @(negedge iKEY[1] or negedge iKEY[2]) because it will generate weird synthesis results. It looks like you intend to have a flop. I would recommend the following:

wire enable = !(iKEY[1] && iKEY[2]); // clocking signal
always @(posedge enable) begin // use enable as a clock
  display1 <= aux[3:0];
  display2 <= {2'b00,secondDigit[1:0]};
end

使用裸机测试平台的工作代码:http://www.edaplayground.com/s/6/245

Working code with bare-bone test-bench : http://www.edaplayground.com/s/6/245

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