在 Verilog 中的 Generate For 循环中实例化模块 [英] Instantiate Modules in Generate For Loop in Verilog

问题描述

我正在尝试使用 generate 块在 Verilog 中实例化一些模块，因为我将实例化它们的可变数量.

I'm trying to instantiate some modules in Verilog using a generate block since I'm going to be instantiating a variable amount of them.

genvar i;
generate
    for (i=1; i<=10; i=i+1) begin
    status whatever_status (
        .clk(clk),
        .reset_n(reset_n),
        .a(a[i]),
        .b(b[i]),
        .out(out[i])
    );
end 
endgenerate

a &b 被声明为父模块的输入数组，out 被声明为一个连线数组.

a & b are declared as input arrays to the parent module and out is declared as a array of wires.

我在这里做错了什么?这在 Verilog 中是不允许的吗?Quartus 告诉我:

What am I doing wrong here? Is this not allowed in Verilog? Quartus is telling me:

Error (10644): Verilog HDL error at driver.v(63): this block requires a name

第 63 行是上面的 for 循环.任何帮助表示赞赏！

Line 63 is the for loop above. Any help is appreciated!

推荐答案

您可以将标签标识符应用于 begin-end 块，并在开始后使用冒号(例如:begin : label - end.这一直是生成块的可选功能，尽管强烈推荐.Quartus 不应该给出错误.

You can apply label identifier to begin-end block with a colon after the begin (example: begin : label - end. This has always been an optional feature for generate blocks, though it is highly recommended. Quartus should not be giving an error.

满足 Quartus 是一个简单的解决方法——添加一个你想要的任何名称的标签:

It is an easy fix to satisfy Quartus-- add a label of any name you want:

genvar i;
generate
    for (i=1; i<=10; i=i+1) begin : generate_block_identifier // <-- example block name
    status whatever_status (
        .clk(clk),
        .reset_n(reset_n),
        .a(a[i]),
        .b(b[i]),
        .out(out[i])
    );
end 
endgenerate

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