如何编写正则表达式以匹配 Verilog 文件中的模块实例化? [英] How do I write a regex to match the module instantiation in a Verilog file?

问题描述

我正在做一个项目，通过使用 perl 脚本语言来促进 verilog 编程.现在我想写一个脚本来扫描一个顶级的verilog文件，然后生成模块的层次列表，这表明我需要提取模块实例verilog 文件中的语句，这里是问题:

I am working on a project to facilitate verilog programming by using perl scripting language. Now I want to write a script to scan a top verilog file, and then generate the hierarchy list for the module, which suggests that I need to extract the module instantiation statement from the verilog file, here is the problem:

如何编写正则表达式来匹配verilog文件中的模块实例，因为我们需要知道顶层模块文件的子模块名称.

How to write a regular expression to match the module instantiation in a verilog file, since we need to know the submodule names of the top module file.

推荐答案

SYNOPSIS="nofollow noreferrer">Verilog::Netlist 展示了如何读入 Verilog 文件并在整个层次结构中查找模块.虽然您可以在某些有限的情况下使用正则表达式，但从长远来看，使用这个 CPAN 解析器模块是值得的.

The SYNOPSIS of Verilog::Netlist shows how to read in a Verilog file and find modules throughout the hierarchy. Although you could use regular expressions in some limited cases, it would be worthwhile to use this CPAN parser module in the long run.

这是我不久前在 PerlMonks 上发布的一些示例代码:verilog perl 用法(Verilog::网表)

Here is some example code I posted on PerlMonks a while back: verilog perl usage (Verilog::Netlist)

vhier 脚本，它是 Verilog-Perl 发行版也很方便.

The vhier script which is part of the Verilog-Perl distribution is also handy.

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