Verilog:是否可以进行索引实例化? [英] Verilog: is it possible to do indexed instantiation?

问题描述

我有一个文件，类似于

module AB(A,B,Out);
  input A,B;
  output Out;

  wire Out;
  assign Out = A & B;
endmodule

我需要使用 N 个这个计算.即我有 a=1001;b=0001，我需要做类似按位与的操作，我有 N 位.

I need to use N number of this calculation. ie i have a=1001; b=0001, I need to do something like bitwise AND, and I have N bits.

我已将其用作实例化:

op[0] = a[0] & b[0];
op[1] = a[1] & b[1];
op[2] = a[2] & b[2];
op[3] = a[3] & b[3];
op[4] = a[4] & b[4];

当我尝试使用索引 i 执行此操作时，我有:

When I'm trying to do this with an index i, I have:

AB g(a[i],b[i],Op[i]) for i = 0 to N-1. 

如果我这样做，它会说 AB 未声明.

If I do this, it says AB is undeclared.

这不可能吗?如果是这样，替代方案是什么?

Is this impossible? If so, what is the alternative?

推荐答案

您有几个选择:

• 参数化模块中的总线大小
• 实例数组
• 生成语句

但是要回答这个问题，可以做实例数组.下面是 AB 模块的语法.

But to answer the question, it is possible to do arrays of instances. Here's what the syntax looks like for your AB module.

module testbench ();
   localparam WIDTH = 4;

   reg [WIDTH-1:0] a_in, b_in;
   wire [WIDTH-1:0] out_a;

   AB u0[WIDTH-1:0]
     (
      .A(a_in),
      .B(b_in),
      .Out(out_a)
     );

   initial begin
      ...
   end

endmodule

这里将a_in[3]、b_in[3]和out_a[3]映射到u0的端口[3].

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