verilog 模块的条件实例化 [英] Conditional instantiation of verilog module

问题描述

是否可以在 verliog 中有条件地实例化模块?

Is it possible to instantiate a module conditionally in verliog ?

例子:

if (en==1)  
  then module1 instantiation  
else  
  module2 instantiation  

推荐答案

来自 IEEE Std 1364-2001:

From IEEE Std 1364-2001 :

12.1.3.3 generate-conditional generate-conditional 是一个 if-else-if 生成构造，它允许模块、用户定义的原语、Verilog 门原语、连续分配、初始块和总是阻塞有条件地实例化到另一个模块中基于设计时确定性的表达式详细说明.

12.1.3.3 generate-conditional A generate-conditional is an if-else-if generate construct that permits modules, user defined primitives, Verilog gate primitives, continuous assignments, initial blocks and always blocks to be conditionally instantiated into another module based on an expression that is deterministic at the time the design is elaborated.

LRM 中给出的示例:

example given in LRM :

module multiplier(a,b,product);
parameter a_width = 8, b_width = 8;
localparam product_width = a_width+b_width; // can not be modified
// directly with the defparam statement
// or the module instance statement #
input [a_width-1:0] a;
input [b_width-1:0] b;
output [product_width-1:0] product;

generate
    if((a_width < 8) || (b_width < 8))
        CLA_multiplier #(a_width,b_width) u1(a, b, product);
        // instantiate a CLA multiplier
    else
        WALLACE_multiplier #(a_width,b_width) u1(a, b, product);
        // instantiate a Wallace-tree multiplier
endgenerate
// The generated instance name is u1

endmodule

这篇关于verilog 模块的条件实例化的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！