未知的 verilog 错误“期待“结束模块"" [英] Unknown verilog error 'expecting "endmodule"'

问题描述

在 verilog 中，我有一个无法克服的错误.这是代码的第一位，然后是最后一位

<块引用>

 模块解码器(op,funct,aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype);输入 [5:0] 操作，函数；输出[2:0] aluop;输出[1:0] btype;输出 mwr、mreg、mrd、alusrc、regdst、regwr；aluop、mwr、mreg、mrd、alusrc、regdst、regwr、btype；案例(操作)6'b000000:开始案例(功能)6'b001010:分配 aluop = 3'b010;6'b001100:分配 aluop = 3'b111;6'b010001:分配 aluop = 3'b011;默认:分配 aluop = 3'b000;尾箱分配 btype = 2'b00;分配 mwr = 1'b0;分配 mreg = 1'b0;分配mrd = 1'b0;分配 alusrc = 1'b0;分配 regdst = 1'b1;分配 regwr = 1'b1;结尾

...

<块引用>

 默认:开始分配 aluop = 3'b000;分配 mwr = 0;分配 mreg = 0;分配mrd = 0;分配 alusrc = 0;分配 btype = 2'b00;分配 regdst = 0;分配 regwr = 0;结尾尾箱

结束模块

它不断给我以下错误

错误 (10170):Decoder.v(7) 文本case"附近的 Verilog HDL 语法错误；期待结束模块"错误 (10170):Decoder.v(14) 文本6"附近的 Verilog HDL 语法错误；期待结束模块"

它也在每个 end 语句、default 和 endcase 中执行此操作

我不知道为什么要这样做，我对 verilog 还很陌生.

提前致谢

解决方案

我相信你只被允许使用 case 语句或 if/else总是 阻止.我不知道为什么您的错误消息没有说明一些更有帮助的内容，但这很可能是问题所在.

尝试重写您的代码，如下所示:

//将wire类型改为reg类型总是 @*开始案例(op)6'b000000:开始aluop = 3'b000结尾...尾箱结尾

In verilog I have an error that I can't get past. this is the first bit of the code then the last bit

 module Decoder(op,funct,aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype);
  input[5:0] op,funct;
  output[2:0] aluop;
  output[1:0] btype;
  output mwr,mreg,mrd,alusrc,regdst,regwr;
  wire aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype;
  case(op)
      6'b000000: begin
          case(funct)
              6'b001010:
                  assign aluop = 3'b010;
              6'b001100:
                  assign aluop = 3'b111;
              6'b010001:
                  assign aluop = 3'b011;
              default:
                  assign aluop = 3'b000;          
          endcase
          assign btype = 2'b00;
          assign mwr = 1'b0;
          assign mreg = 1'b0;
          assign mrd = 1'b0;
          assign alusrc = 1'b0;
          assign regdst = 1'b1;
          assign regwr = 1'b1;
          end

...

  default: begin
      assign aluop = 3'b000;
        assign mwr = 0;
        assign mreg = 0;
        assign mrd = 0;
        assign alusrc = 0;
        assign btype = 2'b00;
        assign regdst = 0;
        assign regwr = 0;
        end
endcase

endmodule

it keeps giving me the following errors

Error (10170): Verilog HDL syntax error at Decoder.v(7) near text "case"; expecting "endmodule" Error (10170): Verilog HDL syntax error at Decoder.v(14) near text "6"; expecting "endmodule"

It also does this at every end statement and default and endcase

I have no idea why it's doing this, I'm fairly new to verilog.

thanks in advance

解决方案

I believe you're only allowed to use a case statement or if/else inside of an always block. I'm not sure why your error message doesn't say something a little more helpful, but that is likely to be the problem.

Try rewriting your code like the following:

//change wire types to reg type

always @*
begin
  case (op)
    6'b000000: begin
      aluop = 3'b000
    end
    ...
  endcase
end

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