需要描述的 Verilog 错误 [英] Verilog error expecting a description

问题描述

module controle(clock, reset, funct, opcode, overflow, PCW, PCCondW, PCDataW, PCSrc, EPCW, AluOutW, MemRegW, AluOp, AluSrcA, AluSrcB, BShift, BSrc, ShamtSrc, AW, RegW, RegDst, RegSrc, Loads, Stores, IRW, MemW, IorD, LSE);
input [5:0] opcode, funct;
input overflow, clock;
output reg AW, IRW, MemW, MemRegW, EPCW, AluOutW, PCW, PCCondW, AluSrcA,                                                     BSrc, RegW, LSE, reset;
output reg [2:0] BShift, PCDataW, Loads, PCSrc, RegSrc;
output reg [1:0] ALuSrcB, Stores, AluOp, ShamtSrc, IorD, RegDst;
parameter estado = 2'h00;
always @ (posedge clock)
begin
case(estado)
//cases
endcase
end
endmodule;

尝试编译此代码时出现以下错误:

When trying to compile this code I get the following error:

错误 (10170): controle.v(418) 文本;"附近的 Verilog HDL 语法错误；期待描述

Error (10170): Verilog HDL syntax error at controle.v(418) near text ";"; expecting a description

不知道这是什么意思.

推荐答案

在 endmodule 关键字(最后一行)之后不应该使用分号:

After endmodule keyword (last line) you should not use a semicolon:

module controle(...);
  ...
endmodule

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