“多个恒定驱动器"Quartus Prime 的 Verilog 错误 [英] "Multiple Constant Drivers" Error Verilog with Quartus Prime
问题描述
我正在用 Verilog 设计一个有限状态机来表示堆栈.模块如下:
I am working on designing a finite state machine in Verilog to represent a stack. The module is as follows:
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output reg OF_Err = 0, UF_Err = 0;
reg [2:0] y, Y;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
always @(s, y, Enable)
if (Enable)
begin
case (y)
A: if (s == 3'b000) Y = B;
else
begin
Y = A;
UF_Err = 1;
end
B: if (s == 3'b000) Y = C;
else if (s == 3'b001) Y = A;
else
begin
Y = B;
UF_Err = 1;
end
C: if (s == 3'b000) Y = D;
else if (s == 3'b100) Y = C;
else Y = B;
D: if (s == 3'b000) Y = E;
else if (s == 3'b100) Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
OF_Err = 1;
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
always @(negedge Resetn, posedge Clock)
begin
if (Resetn == 0)
begin
y <= A;
OF_Err = 0; //Problem
UF_Err = 0; //Problem
end
else y <= Y;
end
OF_Err 和 UF_Err 分别是上溢和下溢错误的指示器.
OF_Err and UF_Err are indicators of overflow and underflow errors, respectively.
但是，我在编译我的项目时遇到以下错误:
However, I get the following errors when compiling my project:
错误 (10028):无法在 state_machine.v(59) 处为 net "OF_Err" 解析多个常量驱动程序错误 (10029):state_machine.v(10) 上的常量驱动程序错误 (10028):无法在 state_machine.v(59) 处为网络UF_Err"解析多个常量驱动程序
这些仅在我添加注释行后出现.我想在 FSM 重置时重置上溢和下溢指示器，但我无法按照我的方式进行.我该怎么做?
These only appeared after I added the commented lines. I want to reset the over- and underflow indicators when the FSM is reset, but I can't do it the way I have it. How do I go about doing this?
(如果它有任何价值，这将在 Altera DE2-115 上执行).
(If it's of any value, this is to be executed on an Altera DE2-115).
推荐答案
正如其他人已经指出的，OF_Err 和 UF_Err 是由两个非法的always块驱动的用于合成.我建议像 Arvind 建议的那样创建两个额外的变量 of_Err 和 uf_Err.但是我建议将 OF_Err 和 UF_Err 保留为失败.
As others have already pointed out, OF_Err and UF_Err were driver by two always blocks which is illegal for synthesis. I recommend creating two additional variables of_Err and uf_Err like Arvind suggested. However I recommend keeping OF_Err and UF_Err as flops.
组合块中的 if (Enable) 推断 Y,c 和 *_Err 作为级别敏感的锁存器.我非常怀疑这是你的意图.我建议将 if (Enable) 移动到同步始终块中，并将组合逻辑保持为纯组合.
The if (Enable) in the combinational block infers Y,c and the *_Err as level-sensitive latches. I highly doubt this is what you intendeds. I recommend moving the if (Enable) into synchronous always block and keeping the combinational logic as pure combinational.
c 是一个简单的赋值，因此将它作为一个连线而不是一个带有简单赋值语句的 reg 可能更有意义.它可以在组合块中，但我更喜欢将组合输入与输出分开.
c is a simple assignment, so it might make more sense having it as a wire instead of a reg with a simple assign statement. It can be in the combinational block, but I prefer to separate combinational input from output.
您确实正确使用了 @(s, y, Enable)，但是 @* 或同义的 @(*) 被推荐用于组合块.@* 是一个自动敏感度列表，它可以节省您的输入和维护，并消除忘记信号的风险.
You did use @(s, y, Enable) correctly, however @* or the synonymous @(*) is recommenced for combinational block. @* is an auto sensitivity list which saves you typing, maintenance, and removes the risk of forgetting a signal.
always @*
begin
of_Err = OF_Err; // <-- default values
uf_Err = UF_Err;
case (y)
// ... your original case code with OF_Err/UF_Err renamed to of_Err/uf_Err
endcase
end
always @(posedge Clock, negedge Resetn) // style difference, I prefer the clock to be first
begin
if (Resetn == 1'b0)
begin
y <= A;
OF_Err <= 1'b0;
UF_Err <= 1'b0;
end
else if (Enable)
begin
y <= Y;
OF_Err <= of_Err;
UF_Err <= uf_Err;
end
end
assign c[1:0] = y[1:0];
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