Verilog 多个驱动程序 [英] Verilog multiple drivers

问题描述

我正在尝试使用 Verilog 制作 BCD 计数器，该计数器将连接到 7 段解码器.
合成后，错误发生如下:

单元中的多源在信号<BCD0 3 >;此信号连接到多个驱动程序.>**还有更多.....

***任何解决方案?*(下面是我的代码)

I'm trying to make BCD Counter using Verilog that will be connected to 7-segment decoder.
After I synthesize it, the error occured like this:

Multi-source in Unit <BCDcountmod> on signal <BCD0<3>>; this signal is connected to multiple drivers.>**And more.....

***Any solution?* (Here's my code below)

module BCDcountmod(
  input Clock, Clear, up, down,
  output [3:0] BCD1_1, BCD0_0 );
reg [3:0] BCD1, BCD0;
//reg [3:0] BCD1_1, BCD0_0;
always @(posedge Clock) begin
  if (Clear) begin
    BCD1 <= 0;
    BCD0 <= 0;
    end
end


 always @(posedge up) begin
      if (BCD0 == 4'b1001) begin
        BCD0 <= 0;
        if (BCD1 == 4'b1001)
          BCD1 <= 0;
        else
          BCD1 <= BCD1 + 1;
      end
      else
        BCD0 <= BCD0 + 1;
    end


always @(posedge down) begin
      if (BCD0 == 4'b0000) begin
        BCD0 <= 4'b1001;
        if (BCD1 == 4'b1001)
          BCD1 <= 4'b1001;
        else
          BCD1 <= BCD1 - 1;
      end
      else
        BCD0 <= BCD0 - 1;
    end

 assign BCD1_1 = BCD1;
 assign BCD0_0 = BCD0;

endmodule

推荐答案

只是为了添加到 mcleod_ideafix 的答案，你有这个块:

Just to add to mcleod_ideafix's answer you have this block:

always @(posedge Clock) begin
  if (Clear) begin
    BCD1 <= 0;
    BCD0 <= 0;
    end
end

这意味着同步清除，我不确定这是否是您的意图，因为通常您会在 ASIC 设计中为触发器进行异步清除，或者为 FPGA 设置初始状态.

Which implies a synchronous clear, I am not sure if that is your intention as typically you would have an asynchronous clear for you flip-flops in ASIC design, or set initial state for FPGA.

对于具有异步高电平有效清除的触发器

For a flip-flop with an asynchronous active-high clear

always @(posedge clock or posedge clear) begin
  if (clear) begin
    BCD1 <= 'b0;  //NB: defined widths
    BCD0 <= 'b0;
  end
  else
    // normal logic
  end
end

更典型的是使用低电平有效复位:

It is more typical to use active-low resets:

always @(posedge clock or negedge clear_n) begin
  if (~clear_n) begin
    BCD1 <= 'b0;  //NB: defined widths
    BCD0 <= 'b0;
  end
  else
    if (up == 1'b1) begin
      // up logic
    end
    else if (down == 1'b1) begin
      // down logic
    end
    else begin 
      // nothing to see here
    end
  end
end

与 == 1'b1 进行比较意味着如果 LHS(左侧)比 1 位宽，您将收到宽度不匹配警告而不是奇怪的行为.

Doing comparisons with == 1'b1 means you will get a width mismatch warning instead of weird behaviour if the LHS (left hand side) is wider than 1 bit.

我还注意到你有:

output [3:0] BCD1_1, BCD0_0 );
reg [3:0] BCD1, BCD0;
assign BCD1_1 = BCD1;
assign BCD0_0 = BCD0;

您只需要执行以下操作即可将 reg 作为输出:

You just needed to do the following to have reg's as outputs:

output reg [3:0] BCD1, BCD0

虽然我发现以下内容更清楚:

Although I find the following much clearer:

output reg [3:0] BCD1,
output reg [3:0] BCD0

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