Verilog中的恒定填充 [英] Constant padding in Verilog

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本文介绍了Verilog中的恒定填充的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

这是有问题的行为Verilog代码示例

Here is the example behavioral Verilog code in question

module constant;
    reg [7:0] foo;
    initial begin
        foo = 1'bz;
        $display("%H", foo);
    end
endmodule

Icarus Verilog给了我

Icarus Verilog gave me

$ iverilog -o constant constant.v
$ ./constant
0Z

但是,根据此网站(以及FPGA课程的讲师正在服用),

However, according to this website (and the lecturer of an FPGA course I am taking),

如果number小于大小常量,则将其用零填充到左侧.如果指定数字的最高有效位具有未知(x)或高阻抗(z)值,则该值将用于向左填充.

If number is smaller than the size constant, then it will be padded to the left with zeros. If the most significant bit of a specified number has an unknown (x) or high-impedance (z) value, then that value will be used to pad to the left.

在这种情况下,输出应为ZZ而不是0Z.我很确定这是由于规范的更改(也许是Verilog 1995中的ZZ和Verilog 2001中的0Z或其他原因),但是导致每种行为的标准是什么?我曾尝试在网上搜索该规范,但似乎没有免费提供,例如需要购买或订阅的.

In that case, the output should be ZZ instead of 0Z. I am pretty sure this is due to a change in the specification (maybe it's ZZ in Verilog 1995 and 0Z in Verilog 2001, or whatever), but what are the standards that result in each behavior? I have tried searching online for the specification, but they don't seem to be freely available, like this one which requires purchasing or a subscription.

作为奖励,我在哪里可以找到各种Verilog规格变化的摘要?

As a bonus, where can I find a summary of changes across various specifications of Verilog?

推荐答案

SystemVerilog IEEE 1800-2017说:

SystemVerilog IEEE 1800-2017 says:

如果无符号数的大小小于为文字常量指定的大小,则无符号数应在左边用零填充.如果无符号数中最左边的位是x或z,则应分别使用x或z填充到左侧.如果无符号数字的大小大于为文字常量指定的大小,则无符号数字应从左侧截断.

If the size of the unsigned number is smaller than the size specified for the literal constant, the unsigned number shall be padded to the left with zeros. If the leftmost bit in the unsigned number is an x or a z, then an x or a z shall be used to pad to the left, respectively. If the size of the unsigned number is larger than the size specified for the literal constant, the unsigned number shall be truncated from the left.

但是,这里的数字不小于大小常数-这里的大小是1'bz中的"1".

However, the number here is not smaller than the size constant - the size here is the "1" in 1'bz.

关于表达结果的转换,标准说:

In terms of conversions of expression results, the standard says:

从较少数量的位到较大数量的位的自动类型转换涉及零扩展(如果无符号)或符号扩展(如果有符号).从大量位数到少量位数的自动类型转换涉及到最高有效位(MSB)的截断.

Automatic type conversions from a smaller number of bits to a larger number of bits involve zero extensions if unsigned or sign extensions if signed. Automatic type conversions from a larger number of bits to asmaller number of bits involve truncations of the most significant bits (MSBs).

由于这是一个无符号表达式和结果,因此将1'bz文字表达式扩展为零以适合foo的8位大小.

As this is an unsigned expression and result, the 1'bz literal expression is then zero extended to fit the 8 bit size of foo.

IEEE 1800-2017可供所有人免费从IEEE网站下载.

IEEE 1800-2017 is free to download for everyone from the IEEE webiste.

这篇关于Verilog中的恒定填充的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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