如何在Verilog / System Verilog中读取环境变量？ [英] How do I read an environment variable in Verilog/System Verilog?

问题描述

如何在Verilog中读取环境变量？ （在VCS模拟器上运行）

How do I read an environment variable in Verilog ? (Running on a VCS simulator)

我正在努力完成

File=$fopen("$PATH/FileName","r");

$ PATH是一个环境变量。

$PATH is an environment variable.

推荐答案

您可以使用SystemVerilog DPI来获取环境。
因为 getenv 是每个POSIX平台的标准C库，所以你不需要实现你自己的 getenv（） code>函数定义的等效函数。

You can simply use SystemVerilog DPI for getting environment. And because getenv is a standard C library for every POSIX platform, so you do not need to implement your own getenv() equivalent function for the function definition again.

SV中的代码示例。

import "DPI-C" function string getenv(input string env_name);

module top;

  initial begin
    $write("env = %s\n", {getenv("HOME"), "/FileName"});
  end
endmodule

运行

ncverilog -sv dpi.v

或

vcs -sverilog dpi.v

它将显示

env = /home/user/FileName

在您的原始问题中还有一个问题，PATH是可执行搜索路径的环境，并与：字符连接。我认为这应该是一个例子，而不是真正的PATH环境。否则，您的fopen文件名可能是/ bin：/ usr / bin：/ usr / local / bin / FileName，这是错误的。

And one more issue in your original question, PATH is a environment for executable search path and concatenate with ":" character. I think it should be an example here, not really "PATH" environment. Otherwise, your fopen file name could be "/bin:/usr/bin:/usr/local/bin/FileName", which is wrong.

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