如何在Verilog中定义多行宏? [英] how to define a multi line macro in verilog?
问题描述
我对verilog(VHDL用户)比较陌生，为了提高自己的技能，我使用verilog(我的QC使用自己的环境)构建了测试环境.
I am relatively new to verilog (a VHDL user), and in order to improve my skills i built my test environment using verilog (my QC use their own env).
在我的环境中，我模拟了一个强制在线上随机刺激的主机(i2c主机).
In my env, I emulate a master that force random stimuli on the lines (i2c master).
由于我并不是真的想使用一个真正的master，而只想要一个表现良好"的master，所以我创建了以下宏来为我提供i2c通信:
since i didn't really want to use a real master and wanted only a 'well behaved' master, i created the following macros to provide me with the i2c communications:
`define writeChipId(addr)\
sda = 1\
#7500 sda = addr[3];\
#2500 sda = addr[2];\
#2500 sda = addr[1];\
#2500 sda = addr[0];\
#2500;
`define writeData(data)\
sda = data[7]\
#2500 sda = data[6];\
#2500 sda = data[5];\
#2500 sda = data[4];\
#2500 sda = data[3];\
#2500 sda = data[2];\
#2500 sda = data[1];\
#2500 sda = data[0];\
#2500 sda = 1;\
#2500; // time for the slave to answer
`define readData\
#sda = 1\
#20000 sda = 0;\
#2500; // master always answer ACK
我的问题是，当我尝试使用这些宏时，出现编译错误(使用modelsim)，说我有语法错误，并且我有意外的'['应该是';'.用于使用chipID宏，并具有意外的#"应为;"使用读\写宏时.
my problem is that, when i try to use these macros i get a compilation errors (using modelsim) saying i have a syntax error and i have unexpected '[' that should be ';' for using the chipID macro and having unexpected '#' that should be ';' when using the read\ write macros.
我尝试(失败)的用法
`writeChipId(`chipID)
和
`writeData(rndData)
和
`readData
最后但并非最不重要的一点:如果我在代码中编写了没有宏的相同行，那么它可以完美编译(仅在一个地方尝试过，不想在其他12个地方这样做，我需要这些宏...)
last, but not least: if i write the same lines without the macro in my code, it compiles perfectly (only tried in one place, don't want to do it for the 12 other places i'll need these macros...)
有人知道这是什么问题吗?我一直在尝试没有运气的宏，并且还验证了它们中间没有空格.
还寻找了多行宏示例，并发现了与我所做的类似的事情，但都没有给出答案.
anyone have a clue what is the problem? i've been trying to play with the macros with no luck and also verified they have no white spaces stuck in the middle.
also looked for multi-line macro examples and found similar things to what I did that didn't give an answer.
提前感谢所有回复者
修改
我忘了说些什么:当我使用宏并删除输入并使用const值而不是输入时，它可以正常工作.
edit
something i forgot saying: when i take the macro and remove the input and use const values instead of the input, it works fine.
推荐答案
好，找到解决方案: 每个宏的第一行也应使用分号(;)，并且-在verilog上很难对chipID使用参数，这是通过将输入放入reg并使用reg的位来解决的.
ok, solution found: the first line of each macro should also have semicolon (;), also - the use of parameter for the chipID is hard on the verilog, this was solved by putting the input into a reg and using the reg's bits.
我上次使用宏时并没有遇到这个问题，因为我犯了另一个错误-我将常量的宏定义为具有分号(意思是`define ADD 32'h0;)，当我使用它时，它插入了;上线，看起来还可以.
i didn't come across this problem the previous time I used macros because of another mistake I made - I defined the macro of the constant to have semicolon (meaning `define ADD 32'h0;) and when I used it it inserted the ; to the line and seemed OK.
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