生成要在 Verilog 中编译的多行 [英] Generating multiple lines to be compiled in Verilog

问题描述

我正在处理一个 VGA 学校项目，我将在 FPGA 上综合该项目.我正在与 Xilinx 合作并使用 Verilog 作为 HDL.该项目说我必须生成固定数量的粒子，将它们显示在屏幕上，并且通过使用键盘，我必须控制这些粒子的环境(如风、重力等).

I'm working on a VGA school-project that I'll synthesize on a FPGA. I'm working with Xilinx and using Verilog as a HDL. The project says that I have to generate a fixed number of particles, display them on screen and, by using the keyboard, I'll have to control the environment for these particles (like the wind, gravity etc.).

我可以使用以下方法生成一个大小为 1 像素(大小不重要)的粒子:

I can generate one particle with a size of 1 pixel (size is not important) by using:

  wire p1 =(posx>=part1x[13:4] && posx<=(part1x[13:4]+1) && posy>=part1y[12:4] && posy<=(part1y[12:4]+1));

通过使用:

wire p1 =(posx>=part1x[13:4] && posx<=(part1x[13:4]+1) && posy>=part1y[12:4] && posy<=(part1y[12:4]+1));
wire p2 =(posx>=part2x[13:4] && posx<=(part2x[13:4]+2) && posy>=part2y[12:4] && posy<=(part2y[12:4]+2));
wire p3 =(posx>=part3x[13:4] && posx<=(part3x[13:4]+3) && posy>=part3y[12:4] && posy<=(part3y[12:4]+3));

将创建三个粒子.

例如，我如何在不编写 100 行代码的情况下生成 100 个(或更多)粒子?

How can I, for instance, generate 100 (or more) particles without having to write 100 lines of code?

推荐答案

您可以使用for"循环来生成它.这是一个非常简单的例子:

You can use a "for" loop to generate this. Here is a very simple example:

wire input[100];
wire output[100];
// ...
genvar i; 
generate 
  for (i = 0; i < 100; i = i+1)  begin
    assign output[i] = ~input[i];
  end  
endgenerate  

为了将此应用于您的情况，您可能需要从使用 part1x、part2x 等切换到使用一个大数组"并计算偏移量它基于 i.

In order to apply this to your case, you might need to switch from using part1x, part2x etc., to using one big "array" and calculate offsets to it based on i.

希望有帮助.祝你好运！

Hope it helps. Good Luck!

这篇关于生成要在 Verilog 中编译的多行的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！