verilog中的任务 [英] task in verilog

问题描述

我正在尝试编写一个任务，该任务提供了一个变量 paddr 不同的值:

I am trying to write a task that gives a variable paddr diffrent values:

module paddr1 ;
task paddr1;
input [10:0]paddr;
input clock;

 @(posedge clock)
begin
paddr=10
#100; 
paddr=20; 
#100; 
paddr=30; 
#100;  
paddr=40;
#100;   
paddr=50;
#100;   
paddr=60;
#100;  
paddr=70;
#100; 
paddr=80;
#100;

end
endtask
endmodule

我尝试从测试台调用此任务并写道:paddr1 (paddr,clock);

I tried to call this task from test bench and wrote: paddr1 (paddr,clock);

编译通过但是当我尝试运行模拟时，我得到了一个错误消息:未解决的对paddr1"的引用.谢谢您的回答任务在一个不同的文件中，然后是测试台

It passes compilation But when I'm trying to run simulation I get an eror massage: Unresolved reference to 'paddr1'. Thank you for your answer the task is in a diffrent file then the test bench

谢谢亚尼夫

推荐答案

您在模块中有一项任务.那么，您是否在测试平台中实例化了模块?如果你这样做了，那么你需要查看模块内部来调用任务:

You've a task inside a module. So, did you instantiate the module in the testbench? If you did, then you'll need to peek inside the module to call the task:

module tb();

  paddr1 U0; // instantiate module with the task in it...

  initial begin
     U0.paddr1(paddr,clock);
  end

endmodule

不过，您的问题要严重得多.在 verilog 中，参数按值传递给任务.这意味着时钟"的值将在任务调用的生命周期内固定.您的任务将永远找不到时钟的边缘，并且将永远等待.此外，您正在分配一个任务输入，这是没有用的.

You've far more serious problems though. In verilog, arguments are passed to tasks by value. This means that the value of 'clock' will be fixed for the lifetime of the call to the task. Your task will never find a posedge of clock, and will wait forever. Also, you're assigning to a task input, which is not useful.

这篇关于verilog中的任务的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！