verilog中的优先编码器 [英] Priority encoder in verilog

问题描述

我对 verilog 有点陌生，我尝试运行此代码但它给了我一个错误:

I am somewhat new to verilog, I tried running this code but it gives me an error:

module enc(in,out);
  input [7:0] in;
  output [3:0] out;
  reg i;
  reg [3:0] out;

  always @*
    begin
      for (i=0;i<7;i=i+1)
        begin
          if ((in[i]==1) && (in[7:i+1]==0))
            out = i;
          else
            out = 0;
        end
    end
endmodule

我认为它抱怨 in[7:i+1] 但我不明白为什么?有人可以请指教..

I think it complains about in[7:i+1] but i don't understand why ? Can someone please advise..

编辑好的，所以我不愿意使用 X，因为它们有很多问题.我正在考虑将代码修改为这样的:

EDIT ok so I am reluctant to using the X due to their numerous problems.. I was thinking of modifying the code to something like this :

module enc(in,out);
  input [7:0] in;
  output [2:0] out;
  reg i;
  reg [2:0] out,temp;

  always @*
    begin
      temp = 0;
      for (i=0;i<8;i=i+1)
        begin
          if (in[i]==1)
            temp = i;
        end
      out = temp;
    end
endmodule

你认为这会奏效吗?我目前无法访问模拟器..

Do you think that will do the trick ? I currently don't have access to a simulator..

推荐答案

优先编码器意味着如果两个或更多位满足标准，则将优先权赋予一位.查看您的代码，您似乎希望在使用递增计数器时优先考虑 LSB.out 在每次look 中都被赋值，所以即使你能编译，最终结果也会是6 或0.

A priority encoder mean giving priority to a one bit if two or more bits meet the criteria. Looking at your code, it appears you wanted to give priority to a LSB while using a up counter. out is assigned in every look, so even if your could compile, the final result would be 6 or 0.

对于 LSB 优先级编码器，首先从 out 的默认值开始，并使用递减计数器:

For an LSB priority encoder, first start with a default value for out and use a down counter:

module enc (
    input wire [7:0] in,
    output reg [2:0] out
  );
  integer i;
  always @* begin
    out = 0; // default value if 'in' is all 0's
    for (i=7; i>=0; i=i-1)
        if (in[i]) out = i;
  end
endmodule

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