如何检查Verilog中的未知逻辑? [英] How to check unknown logic in Verilog?
问题描述
我正在以 6n+1 或 6n-1 的形式检查数字的素性.我有下面的代码,但它似乎没有生成正确的结果.
I'm checking primality of a number in a form of 6n+1 or 6n-1. I have the below code, but it doesn't seem to be generated correct result.
module prime(clk, rst, start, A, ready, P);
input clk, rst, start;
input [7:0] A;
output ready, P;
reg ready, P;
reg [7:0] divisor;
reg val;
always @ (posedge clk or negedge rst) begin
if (!rst) begin
P <= 1'bx;
end
else if (start)
begin
case (A)
-1 : P <= 1;
0 : P <= 1;
1 : P <= 1;
2 : P <= 1;
3 : P <= 1;
5 : P <= 1;
endcase
if (A%2 == 0 && A != 2) begin
P <= 0;
ready <= 1;
end
else if(A > 6)
begin
for(divisor = 5; divisor <= A/divisor; divisor=divisor+6) begin
if (A%divisor == 0 || A%(divisor+2) == 0) begin
P <= 0;
end
end
if (P != 0 && P == 1'bx) begin // need to fix
P <= 1;
end
end
end
end
endmodule
关键是这部分似乎不起作用:
The point is that this part doesn't seem to be working:
if (P != 0 && P == 1'bx)
如何检查变量是否包含未知逻辑,即 x.如上检查
How can I check whether a variable includes unknown logic, meaning x. Checking as the above
P == 1'bx
似乎不起作用.
推荐答案
你应该使用 case equal
运算符 (====
),它测试 4-state 逻辑相等,然后是逻辑相等
运算符(==
).
You should rather use case equality
operator (===
), which tests 4-state logical equality, then logical equality
operator (==
).
对于 ==
运算符,结果为 x
,如果任一操作数包含 x
或 z
>.对于 ===
运算符位,x
和 z
包含在比较中.
For the ==
operator, the result is x
, if either operand contains an x
or a z
.
For the ===
operator bits with x
and z
are included in the comparison.
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