Verilog 中的 FSM 状态变化 [英] FSM state changes in Verilog

问题描述

我看到以下用于在 Verilog 模块中进行状态更改:

I have seen the following used to make state changes in Verilog modules:

state <= 2'b10;

state <= #1 IDLE;

为什么使用 <= 而不仅仅是 =?使用#1 的目的是什么?有区别吗?

Why is <= used and not just =? What is the purpose of using #1? Does it make a difference?

以下是 FSM 的一些 Verilog 代码，显示了正在使用的第一个代码.如果换成第二个，效果会一样吗?

Here is some Verilog code for a FSM that shows the first one being used. Would it work the same if it was replaced with the second?

module fsm( clk, rst, inp, outp);

   input clk, rst, inp;
   output outp;

   reg [1:0] state;
   reg outp;

   always @( posedge clk, posedge rst )
   begin
   if( rst )
       state <= 2'b00;
   else
   begin
       case( state )
       2'b00:
       begin
            if( inp ) state <= 2'b01;
            else state <= 2'b10;
       end

       2'b01:
       begin
            if( inp ) state <= 2'b11;
            else state <= 2'b10;
       end

       2'b10:
       begin
            if( inp ) state <= 2'b01;
            else state <= 2'b11;
       end

       2'b11:
       begin
            if( inp ) state <= 2'b01;
            else state <= 2'b10;
       end
       endcase
   end
end

推荐答案

在像你这样的顺序逻辑 always 块中，最好使用非阻塞赋值 (<=) 而不是阻塞赋值 (=).模拟将更好地代表实际结果逻辑.

In a sequential logic always block like yours, it is better to use non-blocking assignments (<=) instead of blocking assignments (=). Simulations will be better representative of the actual resulting logic.

在纯 RTL Verilog 代码中，如果您对所有时序逻辑都使用非阻塞赋值，则没有理由使用 #1 延迟.

In pure RTL Verilog code, if you are using non-blocking assignments for all sequential logic, there should be no reason to use #1 delays.

我也看到其他人像这样使用 # 延迟.有时是由于在同一个仿真中混合了 RTL 和门网表.其他时候，这样做是为了补偿不良的建模.如果可以，您应该避免在 RTL 代码中使用延迟.

I have also seen others use # delays like this. Sometimes it is due to mixing RTL and gate netlists in the same simulation. Other times it is done to compensate for poor modeling. You should avoid using delays in RTL code if you can.

另见:Verilog 合成、编码中的非阻塞赋值致命的风格！

此外，最好使用 parameter 来命名每个状态.如果一个状态被命名为 IDLE 而不是 2'b10 会更有意义.

Also, it is better to use a parameter to name each of your states. It is much more meaningful if a state is named IDLE instead of 2'b10.

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