Verilog 中如何使用函数? [英] How are functions used in Verilog?

问题描述

在我的 FPGA/Verilog 课程中，我的教授只介绍了函数.

In my FPGA/Verilog course, my professor just went over functions.

他是说在函数中，你按程序编写代码.然后，当你想调用这个函数时，你可以在一个 always 块中调用它(即程序化)，或者你可以用赋值语句调用它.

He was saying that within functions, you write the code procedurally. Then, when you want to call the function, you can either call it within an always block (ie, procedurally), or you can call it with an assign statement.

我不明白如何使用过程代码编写函数，然后连续调用.

It doesn't make sense to me how a function can be written with procedural code, but then be called continuously.

如果有人对此(可能)基本问题有任何见解，不胜感激.

If anyone has any insight to this (probably) basic question, it is much appreciated.

推荐答案

它与组合逻辑块几乎完全相同.你这样写，但它被合成为完全不同的东西.考虑以下几点:

It's pretty much exactly the same as combinational logic blocks. You write it that way, but it's synthesized into something completely different. Consider the following:

always @* begin
    a = b + c;
    d = b + a;
end

always @(posedge clk) begin
    out <= d + in; 
end

这与以下内容完全相同:

This is exactly the same thing as:

function integer calc_d(integer b, integer c) begin
    integer a;
    integer d;
    a = b + c;
    d = b + a;
    calc_d = d; 
end
endfunction

always @(posedge clk) begin
    out <= calc_d(b, c) + in;
end

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