在Verilog中声明声明 [英] Assert statement in Verilog

问题描述

我是Verilog的新手，请多多包涵.

I'm completely new to Verilog, so bear with me.

我想知道Verilog中是否有断言语句.在我的测试平台中，我希望能够断言模块的输出等于某些值.

I'm wondering if there is an assert statement in Verilog. In my testbench, I want to be able to assert that the outputs of modules are equal to certain values.

例如，

mymodule m(in, out);
assert(out == 1'b1);

Google搜索给了我一个链接很少，但是它们要么太复杂，要么似乎并没有就是我想要的.

Googling gave me a few links, but they were either too complex or didn't seem to be what I wanted.

推荐答案

有一个用于声明的开源库，名为 OVL .但是，它很重.我从那里想起的一个窍门是创建一个执行断言的模块.

There is an open source library for assertions called OVL. However, it's pretty heavy. One trick I nicked from there is creating a module to do assertions.

module assert(input clk, input test);
    always @(posedge clk)
    begin
        if (test !== 1)
        begin
            $display("ASSERTION FAILED in %m");
            $finish;
        end
    end
endmodule

现在，任何时候想要检查信号时，您要做的就是在模块中实例化一个断言，如下所示:

Now, any time you want to check a signal, all you have to do is instantiate an assertion in your module, like this:

module my_cool_module(input clk, ...);

     ...

     assert a0(.clk(clk), .test(some_signal && some_other_signal));

     ...

endmodule

断言失败时，您将收到如下消息:

When the assertion fails, you'll get a message like this:

ASSERTION FAILED in my_cool_module.a0

display语句中的％m将显示违规断言的整个层次结构，当您在较大的项目中有很多这样的断言时，这很方便.

The %m in the display statement will show the entire hierarchy to the offending assertion, which is handy when you have a lot of these in a larger project.

您可能想知道为什么我要检查时钟的边缘.这是微妙的，但很重要.如果上面的表达式中的some_signal和some_other_signal被分配到不同的always块中，则根据Verilog仿真器调度这些块的顺序，即使很短时间内，表达式可能为false(即使逻辑完全有效).这会给你一个假阴性.

You may wonder why I check on the edge of the clock. This is subtle, but important. If some_signal and some_other_signal in the expression above were assigned in different always blocks, it's possible the expression could be false for a brief period of time depending on the order that your Verilog simulator schedules the blocks (even though the logic was entirely valid). This would give you a false negative.

上面要注意的另一件事是，我使用！==，如果测试值为X或Z，将导致断言失败.如果使用正常的！=，则可能会在某些情况下无提示地给出误报案例.

The other thing to note above is that I use !==, which will cause the assertion to fail if the test value is X or Z. If it used the normal !=, it could silently give a false positive in some cases.

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