Verilog:非法重新声明 [英] Verilog: Illegal redeclaration

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问题描述

我正在尝试使用 ISE 14.7 为 Trust-Hub.org 上提供的一些基准生成一个编程文件.我正在使用包含一系列 verilog 文件的 AES-T100.我从来没有用过 verilog,也好多年没接触过 VHDL.

I am attempting to generate a programming file useing ISE 14.7 for some of the benchmarks provided on Trust-Hub.org. I am working with AES-T100 which contains a series verilog files. I have never worked with verilog and haven't touched VHDL in years.

理论上,trust-hub 提供的 verilog 代码应该可以工作,但是尝试它会导致编译错误

In theory the verilog code provided by trust-hub should work however trying it gives the compile error

ERROR:HDLCompilers:27 - "../../../../../../AES-T100/src/TjIn/TSC.v" line 28 Illegal redeclaration of 'load'

现在,这个错误是不言自明的,但是查看初学者 verilog 教程 here 我可以看到完全相同的变量名称重复.

Now, this error is fairly self explanatory however looking at a beginners verilog tutorial here I can see the exact same repetition of variables names.

下面的 verilog 代码看起来正确还是信任中心代码中存在错误?

Does this verilog code below look correct or is there some error in the trust-hub code?

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:20:01 03/06/2013 
// Design Name: 
// Module Name:    TSC 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module TSC(
    input rst,
    input clk,
    input [127:0] key,
    output [63:0] load
    );

    reg [63:0] load;
    wire [19: 0] counter;

    lfsr_counter lfsr (rst, clk, counter);
    always @ (posedge clk)
        begin
            load[0] <= key[0] ^ counter[0]; 
            load[1] <= key[0] ^ counter[0]; 
            load[2] <= key[0] ^ counter[0]; 
            load[3] <= key[0] ^ counter[0]; 
            load[4] <= key[0] ^ counter[0]; 
            load[5] <= key[0] ^ counter[0]; 
            load[6] <= key[0] ^ counter[0]; 
            load[7] <= key[0] ^ counter[0]; 

            load[8] <= key[1] ^ counter[1]; 
            load[9] <= key[1] ^ counter[1]; 
            load[10] <= key[1] ^ counter[1];    
            load[11] <= key[1] ^ counter[1];    
            load[12] <= key[1] ^ counter[1];    
            load[13] <= key[1] ^ counter[1];    
            load[14] <= key[1] ^ counter[1];    
            load[15] <= key[1] ^ counter[1];    

            load[16] <= key[2] ^ counter[2];    
            load[17] <= key[2] ^ counter[2];    
            load[18] <= key[2] ^ counter[2];    
            load[19] <= key[2] ^ counter[2];    
            load[20] <= key[2] ^ counter[2];    
            load[21] <= key[2] ^ counter[2];    
            load[22] <= key[2] ^ counter[2];    
            load[23] <= key[2] ^ counter[2];    

            load[24] <= key[3] ^ counter[3];    
            load[25] <= key[3] ^ counter[3];    
            load[26] <= key[3] ^ counter[3];    
            load[27] <= key[3] ^ counter[3];    
            load[28] <= key[3] ^ counter[3];    
            load[29] <= key[3] ^ counter[3];    
            load[30] <= key[3] ^ counter[3];                
            load[31] <= key[3] ^ counter[3];                

            load[32] <= key[4] ^ counter[4];    
            load[33] <= key[4] ^ counter[4];    
            load[34] <= key[4] ^ counter[4];    
            load[35] <= key[4] ^ counter[4];    
            load[36] <= key[4] ^ counter[4];    
            load[37] <= key[4] ^ counter[4];    
            load[38] <= key[4] ^ counter[4];    
            load[39] <= key[4] ^ counter[4];    

            load[40] <= key[5] ^ counter[5];    
            load[41] <= key[5] ^ counter[5];    
            load[42] <= key[5] ^ counter[5];    
            load[43] <= key[5] ^ counter[5];    
            load[44] <= key[5] ^ counter[5];    
            load[45] <= key[5] ^ counter[5];    
            load[46] <= key[5] ^ counter[5];                
            load[47] <= key[5] ^ counter[5];                

            load[48] <= key[6] ^ counter[6];    
            load[49] <= key[6] ^ counter[6];                
            load[50] <= key[6] ^ counter[6];    
            load[51] <= key[6] ^ counter[6];    
            load[52] <= key[6] ^ counter[6];    
            load[53] <= key[6] ^ counter[6];    
            load[54] <= key[6] ^ counter[6];    
            load[55] <= key[6] ^ counter[6];

            load[56] <= key[7] ^ counter[7];    
            load[57] <= key[7] ^ counter[7];    
            load[58] <= key[7] ^ counter[7];    
            load[59] <= key[7] ^ counter[7];    
            load[60] <= key[7] ^ counter[7];    
            load[61] <= key[7] ^ counter[7];    
            load[62] <= key[7] ^ counter[7];    
            load[63] <= key[7] ^ counter[7];                
        end

endmodule

编辑我发现这个讨论 here 讨论了 ansi样式标题.我把顶部的模块代码改成这样:

Edit I found this discussion here that talks about the ansi style header. I changed the top of the module code to this:

module TSC(
    input rst,
    input clk,
    input [127:0] key,
     output reg [63:0] load
    );

    //reg [63:0] load;
    wire [19: 0] counter;

它奏效了.上面的样式在旧版本的verilog或其他东西中不起作用吗?他们为什么要发布明显不起作用的经过测试的"代码?

And it worked. Is the style above that didn't work from older versions of verilog or something? Why would they publish 'tested' code that so clearly doesn't work?

推荐答案

像这样声明并移除 reg [63:0] load;

//////////////////////////////////////////////////////////////
    module TSC(
    input rst,
    input clk,
    input [127:0] key,
    output reg[63:0] load
    );

这篇关于Verilog:非法重新声明的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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