为什么在verilog中发生以下重新声明错误? [英] Why does the following redeclaration error happen in verilog?

问题描述

我正在尝试实现一个简单的verilog代码，如下所示:

I'm trying to implement a simple verilog code as below:

module test1(
    input ACLK,
     input RST,
    output test_output1,
    output test_output2
    );

//wire ACLK;
//wire RST;
reg test_output1;
reg test_output2;


assign test_output1 = ACLK;

always @(posedge ACLK or negedge RST)
begin
    if(!RST) 
    begin
        //test_output1 <=0;
        test_output2 <=0;
    end 
    else 
    begin
        //test_output1 <=0;
        test_output2 <=1;
    end
end 


endmodule

当我在Xilinx ISE中尝试将其合成时，出现以下错误消息:

I get the following error message when I try to synthesize it in Xilinx ISE:

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "test1.v" in library work
ERROR:HDLCompilers:27 - "test1.v" line 30 Illegal redeclaration of 'test_output1'
ERROR:HDLCompilers:27 - "test1.v" line 31 Illegal redeclaration of 'test_output2`

我无法解决此错误.任何帮助将不胜感激.

I am unable to resolve this error. Any help would be highly appreciated.

推荐答案

如果在端口列表中声明端口的方向，则还必须声明类型.这称为ANSI样式标头.

If you declare the directional of the port in the portlist, you must also declare the type. This is referred to as an ANSI style header.

还有一个非ANSI样式的标头，用于分隔端口列表，方向和类型.如果您不遵守IEEE1364-1995约定，则必须使用非ANSI样式并且不能声明类型(例如output reg test_output2;是非法的，而output test_output2; reg test_output2;是合法的).由于支持IEEE1364-2001 ANSI和非ANSI样式(非ANSI允许output reg test_output2;).所有现代的Verilog模拟器都是SystemVerilog(IEEE1800)模拟器，因此它是设计人员的选择. (ANSI样式更受欢迎，因为它的键入较少).

There is also a non-ANSI style header that separates the portlist, directional, and type. If you are fallowing IEEE1364-1995 convention then you must use non-ANSI style and you cannot declare the type (e.g. output reg test_output2; is illegal, while output test_output2; reg test_output2; is legal). Since IEEE1364-2001 ANSI and non-ANSI style is supported (and the non-ANSI allows output reg test_output2;). All modern Verilog simulators are SystemVerilog (IEEE1800) simulators, therefore it is the designers choice. (ANSI style is more popular as it is less typing).

ANSI样式标头:

module test1(
  input ACLK,
  input RST,
  output test_output1,
  output reg test_output2 );

非ANSI样式的标头:

Non-ANSI style header:

module test1( ACLK, RST, test_output1, test_output2 );
  input ACLK;
  input RST;
  output test_output1;
  output test_output2;

  reg test_output2;

注意:在IEEE1364中，不能使用assign语句驱动reg，它必须是net类型. IEEE1800简化了规则，建议将其改为logic而不是reg，但是通常如果要使用assign，则应该分配一个网络(例如wire).

Note: With IEEE1364, you can not drive a reg with an assign statement, it must be a net type. IEEE1800 has softened the rule the it is recommenced logic in stead of reg, but generally if you are going to use assign then you should be assigning a net (e.g. wire).

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