Verilog中可综合的算术移位 [英] Synthesizable arithmetic shift in Verilog

问题描述

我最近在stackoverflow上遇到了此答案.

I recently came across this answer on stackoverflow.

使用Verilog，一旦进行了部分选择，结果将是未签名的.在选定的零件上使用 $ signed 系统任务对其进行签名.

With Verilog, once you take a part-select, the result is unsigned. Use the $signed system task on the part select to make it signed.

此方法是否可综合(即系统任务 $ signed )

Is this method synthesizable (ie the system task $signed)

如果它不可合成，是否有另一种方法可以对像 a< = a>>>> 2 这样的变量执行算术移位(当 a除以4).

If it is not synthesizable, is there a different way to perform arithmetic shift on variables like a <= a>>>2 (this should give the quotient when a is divided by 4).

推荐答案

它当然是可合成的.您的特定工具是否支持它是另一个问题.

It certainly is synthesizable. Whether your particular tool supports it is another question.

您还可以在SystemVerilog中使用强制转换.

You can also use a cast in SystemVerilog.

res = signed'(registers[0][0]) >>> 2;

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