不管有符号变量如何，算术移位都作为逻辑移位 [英] Arithmetic shift acts as a logical shift, regardless of the signed variable

问题描述

我有一个这样声明的寄存器:

I've got a register declared as so:

logic signed [15:0][2:0][15:0] registers;

当我将2的恭维数放入数组中并以数学方式对数字进行移位时，它会逻辑上移位:

When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead:

registers[0][0] = 16'b1000000000000000;
registers[0][0] = registers[0][0]>>>2;

显然，如果数字未签名，系统将进行逻辑移位而不是算术移位.但是，您可以清楚地看到，寄存器"绝对是签名的.

Apparently, the system will logical shift instead of arithmetically shift if the number is not signed. However as you can clearly see, 'registers' is definitely signed.

有人知道我在这里可能会想念什么吗?

Does anybody know what I might be missing here?

谢谢！

推荐答案

使用Verilog，进行部分选择后，结果为unsigned.在选定的零件上使用$signed系统任务进行签名.

With Verilog, once you take a part-select, the result is unsigned. Use the $signed system task on the part select to make it signed.

res = $signed(registers[0][0]) >>> 2;

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