Verilog 中的 BCD 加法器 [英] BCD Adder in Verilog

问题描述

我正在尝试用 Verilog 编写 BCD 加法器，但我在使用其中一个模块时遇到了问题.具体来说，就是取两个 BCD 数字并将它们相加的加法器.所以，这个想法是如果两位数之和小于或等于九，那么它是正确的.但是，如果它更大，则必须添加偏移量 6.到目前为止，这是我的 Verilog 代码:

I am trying to write a BCD Adder in Verilog, but I am having trouble with one of the modules. Specifically, the adder that takes two BCD digits and adds them. So, the idea is if the sum of the two digits is less than or equal to nine, then it is correct. However, if it is greater, then an offset of 6 has to be added. Here is my Verilog code so far:

module DIGITADD(
    input [3:0] IN_A,
    input [3:0] IN_B,
    input CIN,
    output reg COUT,
    output reg [3:0] SUM
);

wire s2, c2;

always @ ( * ) 
begin
 assign {c2, s2} = IN_A + IN_B + CIN;

 if(s2 <= 9 && c2 == 0) begin
  assign {COUT, SUM} = {c2, s2};
 end
 else if({c2, s2} > 9) begin
  assign {COUT, SUM} = {c2, s2 + 6};
 end
end
endmodule

无论如何，当我尝试在 Xilinx 中对其进行综合时，出现以下错误:

Anyways, when I try to synthesize it in Xilinx, I get the following errors:

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 对标量线 'c2' 的引用不是合法的 reg 或变量左值

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 Reference to scalar wire 'c2' is not a legal reg or variable lvalue

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 对标量线 's2' 的引用不是合法的 reg 或变量左值

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 Reference to scalar wire 's2' is not a legal reg or variable lvalue

ERROR:HDLCompilers:42 - "DIGITADD.v" line 33 程序分配的左侧非法

ERROR:HDLCompilers:42 - "DIGITADD.v" line 33 Illegal left hand side of procedural assign

我尝试更改一些内容，例如将 wire 更改为 reg，但我仍然无法使其正常工作.任何帮助表示赞赏.

I tried changing some things like changing wire to reg, but I still can't get it to work. Any help is appreciated.

推荐答案

好的，我想通了，正确的代码如下.基本上，请参阅我对我的问题所做的评论，以了解一些要记住的提示.有趣的是，与我之前的混乱相比，这要简单得多.

Okay, I figured it out, the correct code is below. Basically, see the comment I made on my question for some tips to remember. Its funny how much simpler this is compared to the mess I had earlier.

module DIGITADD(
    input [3:0] IN_A,
    input [3:0] IN_B,
    input CIN,
    output COUT,
    output [3:0] SUM
    );

reg [4:0] s2;

assign SUM = s2[3:0];
assign COUT = s2[4];

always @ ( * )
begin
    s2 = IN_A + IN_B + CIN;
    if (s2 > 9)
    begin
        s2 = s2 + 6;
    end
end
endmodule 

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