全 8 位加法器，不合逻辑的输出 [英] Full 8 bit adder, illogical output

问题描述

我创建了一个带有全加器的 8 位加法器.如您所见，我开始从右到左添加相应的位，对于 cin 信号 t1 和 t2，并按顺序输出 t2 和 t1.第一个 cin 设置为加法器输入 cin.我在我的实现中没有看到任何问题，但是当我运行它时，我得到 o 输出信号的红线.有人能告诉我出了什么问题吗?(我已经测试了全加器并返回了正确的结果.)

I have created an 8 bit adder with a fulladder. As you can see, i started adding the bits from the right to left with the corresponding bits and for cin the signals t1 and t2 and cout the t2 and t1 in order. The first cin is set to the adder input cin. I don't see any problems in my implementation, but when i run it, i get red line for the o output signal.Can somebody tell me what is going wrong?(i have tested the fulladder and returns the right results.)

谢谢.

代码如下:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder8bit is
    Port ( a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           cin : in  STD_LOGIC;
           o : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out  STD_LOGIC);
end adder8bit;

architecture Behavioral of adder8bit is

component fulladder is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           o : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end component;

signal t1,t2:std_logic:='0';

begin

C1: fulladder port map( a => a(0), b => b(0), cin => cin, o => o(0), cout => t1 );
C2: fulladder port map( a => a(1), b => b(1), cin => t1, o => o(1), cout => t2 );
C3: fulladder port map( a => a(2), b => b(2), cin => t2, o => o(2), cout => t1 );
C4: fulladder port map( a => a(3), b => b(3), cin => t1, o => o(3), cout => t2 );
C5: fulladder port map( a => a(4), b => b(4), cin => t2, o => o(4), cout => t1 );
C6: fulladder port map( a => a(5), b => b(5), cin => t1, o => o(5), cout => t2 );
C7: fulladder port map( a => a(6), b => b(6), cin => t2, o => o(6), cout => t1 );
C8: fulladder port map( a => a(7), b => b(7), cin => t1, o => o(7), cout => cout );

end Behavioral;

推荐答案

在我看来，您假设您的实例 C1 ... C8 是按顺序执行的，因此您交替使用了两个信号t1 和 t2 就好像这是一个可以重用变量的程序.

It appears to me, that you assume that your instances C1 ... C8 are executed sequentially and therefore you alternate the two signals t1 and t2 as if this was a program where variables can be reused.

然而，您在这里创建了一个带有连接的结构，并且 t1 将是您使用它的所有 8 个实例的相同信号.因此，您有 4 个驱动程序 C1、C3、C5 和 C7 用于 t1(对于 t2 也是如此)和这个代码很可能无法合成.

However you are creating a structure with connections here and t1 will be the same signal for all 8 instances on which you are using it. Therefore you have 4 drivers C1, C3, C5 and C7 for t1 (and similarly for t2) and this code would most likely not be synthesizable.

您可以做的是在设置中使用 8 个进位信号，如下所示:

What you could do is use 8 carry signals in a setup as follows:

signal c: std_logic_vector(7 downto 1) := (others => '0');
-- ...
C1: fulladder port map( a => a(0), b => b(0), cin => cin, o => o(0), cout => c(1) );
C2: fulladder port map( a => a(1), b => b(1), cin => c(1), o => o(1), cout => c(2) );
C3: fulladder port map( a => a(2), b => b(2), cin => c(2), o => o(2), cout => c(3) );
-- ...
C8: fulladder port map( a => a(7), b => b(7), cin => c(7), o => o(7), cout => cout );

此外，您可以查看 foor-generate-loops 减少代码中的重复量.如果扩展进位向量以包含 cin 和 cout，则所有 8 行看起来都相同(除了增加的索引).

Furthermore you could have a look at foor-generate-loops to reduce the amount of repetition in your code. If you extend the carry-vector to include cin and cout, all 8 lines then look the same (except for the increasing indices).

signal c: std_logic_vector(8 downto 0) := (others => '0');
-- ...
c(0) <= cin;
cout <= c(8);
-- ...
-- your for-generate loop here...

这篇关于全 8 位加法器，不合逻辑的输出的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！