通用加法器“推理架构":模拟错误 [英] generic adder "inference architecture": simulation error

问题描述

所以，我必须创建一个带有进位和进位的通用 N 位加法器.到目前为止，我已经制作了两种完全可用的架构，一种使用 generate 函数，一种使用 rtl 描述，如下所示:

So, I have to create a generic N-bit adder with carry in and carry out. I have made two fully working architectures so far, one using the generate function and one using the rtl description as follows:

实体:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder_n is
generic (N: integer:=8);
port (
    a,b: in std_logic_vector(0 to N-1);
    cin: in std_logic;
    s: out std_logic_vector(0 to N-1);
    cout: out std_logic);
end adder_n;

架构 1 和 2:

    --STRUCT
architecture struct of adder_n is
    component f_adder
        port (
            a,b,cin: in std_logic;
            s,cout: out std_logic);
    end component;
signal c: std_logic_vector(0 to N);
begin
    c(0)<=cin;
    cout<=c(N);
    adders: for k in 0 to N-1 generate
        A1: f_adder port map(a(k),b(k),c(k),s(k),c(k+1));
    end generate adders;
end struct;
--END STRUCT

architecture rtl of adder_n is
    signal c: std_logic_vector(1 to N);
begin
    s<=(a xor b) xor (cin&c(1 to N-1));
    c<=((a or b) and (cin&c(1 to N-1))) or (a and b);
    cout<=c(N);
end rtl;

现在，我的问题出在我试图推断加法器的第三种架构中.尽管我创建的以下架构编译得很好，但当我尝试模拟它时，我得到了一个模拟错误(在 Modelsim 上)，我在这篇文章的末尾附上了它.我猜 numeric_std 定义有问题.我试图避免使用 arith 库，但我仍在努力适应 IEEE 标准.欢迎任何想法！！谢谢！

Now, my problem is in the third architecture where I'm trying to infer the adder. Even though the following architecture I created compiles just fine, when I try to simulate it, I get a simulation error (on Modelsim), which I have attached at the end of this post. I'm guessing there's something wrong with the numeric_std definitions. I am trying to avoid the arith library and I'm still trying to get used to the IEEE standard. Any ideas are welcomed!! Thank you!

推理拱:

--INFERENCE

architecture inference of adder_n is
    signal tmp: std_logic_vector(0 to N);
    signal atmp, btmp, ctmp, add_all : integer :=0;
    signal cin_usgn: std_logic_vector(0 downto 0);
    signal U: unsigned(0 to N);
begin

    atmp <= to_integer(unsigned(a));
    btmp <= to_integer(unsigned(b));
    cin_usgn(0) <= cin;
    ctmp <= to_integer(unsigned(cin_usgn));


    add_all <= (atmp + btmp + ctmp);
    U <= to_unsigned(add_all,N);

    tmp <= std_logic_vector(U);
    s <= tmp(0 to N-1);
    cout <= tmp(N); 
end inference;

-- END

模拟错误:

#由于致命错误而无法继续.
# HDL 调用序列:
# 停在 C:/altera/14.1/modelsim_ase/test1_simon/adder_inference.vhd 58 架构推理

# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at C:/altera/14.1/modelsim_ase/test1_simon/adder_inference.vhd 58 Architecture inference

推荐答案

U的长度为N+1(0到N)

The length of U is N+1 (0 to N)

变化

    U <= to_unsigned(add_all,N);

到

    U <= to_unsigned(add_all,N+1);

将防止adder_n 的架构inference 中信号分配的左侧和右侧之间的长度不匹配.

Will prevent a length mismatch between the left hand side and right hand side of the signal assignment in architecture inference of adder_n.

传递给to_unsigned的参数指定了长度.

The passed parameter to to_unsigned specifies the length.

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