全加法器3位std_logic_vector [英] full adder 3-bit std_logic_vector

问题描述

我正在学习vhdl，当我模拟3位全加器时出现错误 用std_logic_vector实现的(因为使用'+'操作的能力) 只是老师给我们的一个例子， 如果这是一个简单的问题，请原谅我... 这是代码:

i am learning vhdl and i get an error when i simulate a 3-bit full adder that implements with std_logic_vector (because of ability to use '+' operation) just an example that our teacher gave us, forgive me if it is a simple question... here is code :

Library ieee;
use ieee.std_logic_1164.all;
entity adder_3_bit is
    port(
    a,b : in std_logic_vector(2 downto 0);
    cin : in std_logic;
    cout : out std_logic;
    sum : out std_logic_vector(2 downto 0)
    );
end adder_3_bit;
architecture behav of adder_3_bit is 
    signal temp : std_logic_vector(3 downto 0);
    begin
    temp <= ('0' & a) + ('0' & b) + ("000" & cin);
    sum <= temp(2 downto 0);
    cout <= temp(3);
    end behav;

当temp试图在2位数组的末尾加0时，我得到一个错误， 它说:

i get an error when temp is trying to add 0's at then end of 2 bit arrays, which it says :

Line 15: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"ERROR:HDLCompiler:854

这里的每个人都是工作代码:

every body here is the working code:

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder_3_bit is
    port (
    a,b : in std_logic_vector(2 downto 0);
    cin : in std_logic;
    cout : out std_logic;
    sum : out std_logic_vector(2 downto 0)
    );
end adder_3_bit;
architecture behav of adder_3_bit is 
    signal temp : std_logic_vector(3 downto 0);
    begin
     temp <= std_logic_vector(('0' & unsigned (a)) + ('0' & unsigned(b)) + ("000" & cin));
    sum <= temp(2 downto 0);
    cout <= temp(3);
end behav;

推荐答案

没有任何其他库，就无法添加类型为std_logic_vector的信号.没有定义带有两个std_logic_vector自变量的+运算符.正确的方法是包括numeric_std程序包，并将您的参数强制转换为unsigned以进行添加.

Without any additional libraries, you cannot add signals of type std_logic_vector. There is no + operator defined that takes two std_logic_vector arguments. The correct way to do this is to include the numeric_std package and cast your arguments to unsigned for your additions.

use ieee.numeric_std.all;

temp <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b) + unsigned("000" & cin));

实际上，大多数人不会为这种简单的操作创建整个实体，因此由于您的信号已经是针对数据的正确类型(数字使用无符号，位的集合使用std_logic_vector)，因此转换次数较少.这就是为什么看起来有点尴尬的原因.

In practice, most people don't create a whole entity for such a simple operation so there are fewer casts as your signals are in the correct type for the data already (numbers use unsigned, collections of bits use std_logic_vector), which is why this looks a bit awkward.

您还可以通过使用概要包(std_logic_unsigned)来做到这一点，它看上去会更干净(没有强制转换)，但是该包不是VHDL标准的一部分，并且已弃用.

You could also get by doing this with the synopsis package (std_logic_unsigned) and it would look a little cleaner (no casts), but that package is not part of the VHDL standard and its use has been deprecated.

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