在变量类型VHDL中添加2个std_logic_vector [英] Adding 2 std_logic_vector in variable type VHDL

问题描述

我正在这个学校的项目中工作. 我有两个std_logic_vector(从31下降到0)A和B，并且我有一个变量类型std_logic_vector(从32下降到0)，我想添加A + B并将结果放入32位的std_logic_vector中.

I'm working in this school project. I have two std_logic_vector (31 downto 0) A and B, and I have a variable type std_logic_vector (32 downto 0) and I want to add A+B and put the result in my std_logic_vector with 32 bits.

这是我的设计

library IEEE;    
use IEEE.STD_LOGIC_1164.ALL;    
USE ieee.numeric_std.ALL;    
use ieee.std_logic_arith.all;

entity Ej3 is
    Port ( A :     in  STD_LOGIC_VECTOR (31 downto 0);   
           B :     in  STD_LOGIC_VECTOR (31 downto 0);    
           S :     out STD_LOGIC_VECTOR (31 downto 0);    
           AluOp : in  STD_LOGIC_VECTOR (3 downto 0);    
           COut :  out STD_LOGIC;   
           Z :     out STD_LOGIC;    
           OFL :   out STD_LOGIC);    
end Ej3;


architecture Behavioral of Ej3 is

    begin

    process(AluOp)    
        variable Temp: STD_LOGIC_VECTOR (32 downto 0);   
    begin

        Temp := A+B;

我有这个错误:找到了运算符"+"的'0'定义，无法确定"+"的确切重载匹配定义

有人可以帮忙吗?

推荐答案

首先，您将标准库numeric_std和非标准库std_logic_arith包括在内.他们彼此冲突，所以摆脱了std_logic_arith.

First of all you've included the standard library numeric_std and the nonstandard library std_logic_arith together. They conflict with each other so get rid of std_logic_arith.

这两个软件包均使用unsigned和signed类型实现算术运算.如果要对向量进行算术运算，强烈建议您使用这些类型.它明确表明您希望它们在数字上下文中进行解释.没有为在std_logic_1164中实现的std_logic_vector类型定义的"+"运算符，这就是为什么会出现错误的原因.您还可以通过包含numeric_std_unsigned在VHDL-2008中使用算术运算符来扩展该类型.同样，最好只使用传统的unsigned类型:

Both of those packages implement arithmetic using the unsigned and signed types. It is strongly recommend that you use these types if you want to do arithmetic on vectors. It makes it explicitly clear that you want them interpreted in a numeric context. There is no "+" operator defined for the std_logic_vector type implemented in std_logic_1164 which is why you get an error. You can augment that type with arithmetic operators in VHDL-2008 by also including numeric_std_unsigned. Again, it is better to just use the traditional unsigned type:

A : in unsigned(31 downto 0);
B : in unsigned(31 downto 0);

...

process(AluOp)
  variable temp : unsigned(32 downto 0);
begin

  temp := resize(A, temp'length) + B;

赋值的左侧和右侧的长度必须匹配，因此首先调整A信号的大小，然后将其扩展为33位，然后再添加32位信号B.

The length of the left and right sides of the assignment have to match so first resize the A signal, expanding it to 33 bits before adding the 32-bit signal B.

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