VHDL中的"std_logic"枚举类型的目的是什么? [英] What is the purpose of the `std_logic` enumerated type in VHDL?

问题描述

std_logic枚举类型的用途是什么?

What is the purpose of the std_logic enumerated type?

'U': uninitialized. This signal hasn't been set yet.
'X': unknown. Impossible to determine this value/result.
'0': logic 0
'1': logic 1
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
'H': Weak signal that should probably go to 1
'-': Don't care. 

推荐答案

std_logic基本上是单根电线或一点.您可以在其上使用逻辑运算符(和，或，或).我相信在模拟设计时，我只会看到"X"，"0"或"1".显然，您想要"0"或"1". "X"表示该值未知(可能未连接任何东西或信号中有毛刺).另外，std_logic_vector可以用于需要大于1位宽的信号.我不确定这是否能回答您的问题...

std_logic is basically a single wire or bit. You can use logical operators (and, or, xor, etc.) on them. When simulating a design I believe I have only seen 'X', '0', or '1'. Obviously you want '0' or '1'. An 'X' indicates that the value is unknown (possibly not connected to anything or there is a glitch in the signal). Also, std_logic_vector can be used for signals that need to be more than 1 bit wide. I'm not sure if this answers your question...

这篇关于VHDL中的"std_logic"枚举类型的目的是什么?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！